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R Vir te x-5 FPGA ML561 Memor y Interfaces De velopment Boar d User Guide UG199 (v1.2) Ap ril 19, 2008.
Virtex-5 FPGA ML561 User Guide www .xilinx.com UG199 (v1.2) April 19 , 2008 Xilinx is disclosing this user gui de, manual, rel ease note, and/or specification (the "Documentation") to y ou solely for use in the de velopment of designs to operate with Xilinx hardw are devices.
Virtex-5 FPGA ML561 User Guide www .xilinx.com 3 UG199 (v1.2) Apr il 19, 2008 Preface: About This Guide Guide Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Additional Documentation .
4 www .xilinx.com Vir tex-5 FPGA ML5 61 User Gu ide UG199 (v1.2) April 19, 2008 R Seven-Segment Displays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Light Emitting Diodes (LE Ds) . . . . . . . .
Virtex-5 FPGA ML561 User Guide www .xilinx.com 5 UG199 (v1.2) Apr il 19, 2008 R Appendix B: Bill of Materials Appendix C: LCD Interface General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6 www .xilinx.com Vir tex-5 FPGA ML5 61 User Gu ide UG199 (v1.2) April 19, 2008 R.
Virtex-5 FPGA ML561 User Guide www .xilinx.com 7 UG199 (v1.2) Apr il 19, 2008 R Pr eface About This Guide This user guide describes the V irtex ® -5 FPGA ML561 Memory Interfaces Development Board. Comple te and up-to-date documentat ion of the V irtex-5 family of FPGAs is available on the Xilinx website at http://www .
8 www .xilinx.com Vir tex-5 FPGA ML5 61 User Gu ide UG199 (v1.2) April 19, 2008 Pref ace: About This Guide R - Configurable Logic Block s (CLBs) -S e l e c t I O ™ R e s o u r c e s - SelectIO Logic.
Virtex-5 FPGA ML561 User Guide www .xilinx.com 9 UG199 (v1.2) Apr il 19, 2008 Con ventions R Con ventions This document uses the following convention s. An example illustrates each convention. T ypographical This document uses the following typographica l conventions.
10 www .xilinx.com Vir tex-5 FPGA ML5 61 User Gu ide UG199 (v1.2) April 19, 2008 Pref ace: About This Guide R Hard ware Measurements These measurements ar e the actual real-time measurements of an eye diagram and a segment of the test pattern (PRB S6) waveform captured on ML561 hardware at the designated probe point using an Agilent scope.
Virtex-5 FPGA ML561 User Guide www .xilinx.com 11 UG199 (v1.2) Apr il 19, 2008 R Chapter 1 Intr oduction This chapter introduces the V irtex ® -5 FPGA ML561 re ference design.
12 www .xilinx.com Vir tex-5 FPGA ML5 61 User Gu ide UG199 (v1.2) April 19, 2008 Chapter 1: Introd uction R Vir te x-5 FPGA ML561 Memory Interfaces Development Boar d A high-level functional bloc k diagram of the V irtex-5 FPGA ML561 Memory Interfaces Development Board is shown in Figur e 1- 1 .
Virtex-5 FPGA ML561 User Guide www .xilinx.com 13 UG199 (v1.2) Apr il 19, 2008 Virtex-5 FPGA ML5 61 Memory Interfaces Development Boar d R Figur e 1-2 shows the V irtex-5 FPGA ML561 Development Board and indicates the locations of the reside nt memory devi ces.
14 www .xilinx.com Vir tex-5 FPGA ML5 61 User Gu ide UG199 (v1.2) April 19, 2008 Chapter 1: Introd uction R.
Virtex-5 FPGA ML561 User Guide www .xilinx.com 15 UG199 (v1.2) Apr il 19, 2008 R Chapter 2 Getting Started This chapter describes the items needed to configure the V irtex-5 FPGA ML561 Memory Interfaces Development Boar d.
16 www .xilinx.com Vir tex-5 FPGA ML5 61 User Gu ide UG199 (v1.2) April 19, 2008 Chapter 2: Getting Star ted R 5. Insert the CompactFlash card included in th e kit into socket J27 on the V irtex-5 FPGA ML561 Development Board. T o select the startu p file, check that SW8 is set to position 0.
Virtex-5 FPGA ML561 User Guide www .xilinx.com 17 UG199 (v1.2) Apr il 19, 2008 R Chapter 3 Hardwar e Description This chapter describes the major har dware blocks on the V irtex-5 FPGA ML 561 Development Board and provides useful des ign consideration.
18 www .xilinx.com Vir tex-5 FPGA ML5 61 User Gu ide UG199 (v1.2) April 19, 2008 Chapter 3: Har dware De scription R FPGA The ML561 uses three V irtex-5 XC5VLX50T -FFG1 136 devices, each in a 1 136-pin, 35 mm x 35 mm BGA package. Figure 1- 1, page 12 shows the memory devices associated with the three FPGAs.
Virtex-5 FPGA ML561 User Guide www .xilinx.com 19 UG199 (v1.2) Apr il 19, 2008 Har dware Ov erview R Memories Ta b l e 3 - 1 lists the typ es of memories that the ML561 board supports.
20 www .xilinx.com Vir tex-5 FPGA ML5 61 User Gu ide UG199 (v1.2) April 19, 2008 Chapter 3: Har dware De scription R DDR2 SDRAM Components The ML561 board contains two 333 MHz Micron M T47H32M16CC-3 (16-bit ) DDR2 SDRAM components that provide a 32-bit inte rface to FPGA #1.
Virtex-5 FPGA ML561 User Guide www .xilinx.com 21 UG199 (v1.2) Apr il 19, 2008 Memory Deta ils R Memory Details DDR400 and DDR2 Component Memor ies The FPGA #1 de vice on the V irt ex-5 FPGA ML 561 Development Board is connected to DDR and DDR2 component memories, as s hown in Figure 3-3 .
22 www .xilinx.com Vir tex-5 FPGA ML5 61 User Gu ide UG199 (v1.2) April 19, 2008 Chapter 3: Har dware De scription R Ta b l e 3 - 3 describes all si gnals associated with DDR400 Component memories. Ta b l e 3 - 4 describes all signals associated with DDR2 Compone nt memories.
Virtex-5 FPGA ML561 User Guide www .xilinx.com 23 UG199 (v1.2) Apr il 19, 2008 Memory Deta ils R DDR2 SDRAM DIMM The FPGA #2 de vice on the V irt ex-5 FPGA ML 561 Development Board is connected to DDR2 memories. The DDR2 memory interface in cludes a 144-bit wide DIMM connection to up to five 240-pin DDR2 DIMM sockets.
24 www .xilinx.com Vir tex-5 FPGA ML5 61 User Gu ide UG199 (v1.2) April 19, 2008 Chapter 3: Har dware De scription R Ta b l e 3 - 5 describes all the signals ass ociated with DDR2 DIMM component memories. For the Deep DIMM interface to four DIMMs , th e individual dedicate d control signal s are listed at the bottom of Ta b l e 3 - 5 .
Virtex-5 FPGA ML561 User Guide www .xilinx.com 25 UG199 (v1.2) Apr il 19, 2008 Memory Deta ils R QDRII and RLDRAM II Memories Figur e 3-5 summarizes the distribution of QDRI I and RLDRAM II component interface signals among the differ ent ba nks of the FPGA #3 device.
26 www .xilinx.com Vir tex-5 FPGA ML5 61 User Gu ide UG199 (v1.2) April 19, 2008 Chapter 3: Har dware De scription R Ta b l e 3 - 6 describes all the signals associated with QDRII component memories. X APP 853 : QDR II SRAM Interface for V i rtex-5 Devices and its corresponding demo are included on the CD shipped with the ML561 T ool Kit.
Virtex-5 FPGA ML561 User Guide www .xilinx.com 27 UG199 (v1.2) Apr il 19, 2008 External Inte rfaces R External Interfaces The external interfaces of the V irtex-5 FP GA ML561 Development Board are described in this section. RS-2 3 2 The ML561 board pr ovides an RS-2 32 serial interface using a Maxim MAX3316ECUP device.
28 www .xilinx.com Vir tex-5 FPGA ML5 61 User Gu ide UG199 (v1.2) April 19, 2008 Chapter 3: Har dware De scription R 200 MHz L VPECL Cloc k The 200 MHz L VPECL clock source is an Epson EG-2121CA200M-PCHS oscillator (Y1) with a differ entia l output. The oscillator runs at 200 MHz ± 100 PPM with an operating voltage of 2.
Virtex-5 FPGA ML561 User Guide www .xilinx.com 29 UG199 (v1.2) Apr il 19, 2008 External Inte rfaces R 33 MHz System A CE Controller Oscillator A single-ended 33 MHz Epson SG-8002CA oscill ator is provided on the board (Y3) as a clock sour ce for System ACE functionality .
30 www .xilinx.com Vir tex-5 FPGA ML5 61 User Gu ide UG199 (v1.2) April 19, 2008 Chapter 3: Har dware De scription R Se ven-Segment Displa ys One seven-segment display per FPGA (for a tot al of three) is available for use.
Virtex-5 FPGA ML561 User Guide www .xilinx.com 31 UG199 (v1.2) Apr il 19, 2008 External Inte rfaces R P ow er On or Off Slide Switch The power on or of f slide switch is a DPST slide swi tch used to apply input power to the board.
32 www .xilinx.com Vir tex-5 FPGA ML5 61 User Gu ide UG199 (v1.2) April 19, 2008 Chapter 3: Har dware De scription R Liquid Cr ystal Displa y Connector Previous memory boar ds such as the ML 461 had a DisplaytechQ 64128E-FC-BC-3LP 64x128 LCD panel.
Virtex-5 FPGA ML561 User Guide www .xilinx.com 33 UG199 (v1.2) Apr il 19, 2008 P ower Regulat ion R The product specification at http://www .displaytech.com.hk/p d f/graphic/64128e%20series-v10.PDF provides more information. Appendix C, “LCD Interface,” describes the LCD operation in detail.
34 www .xilinx.com Vir tex-5 FPGA ML5 61 User Gu ide UG199 (v1.2) April 19, 2008 Chapter 3: Har dware De scription R also be supplied from a bench supply using the two banana jacks: J25 (RED) for +5V and J24 (BLACK) for GND.
Virtex-5 FPGA ML561 User Guide www .xilinx.com 35 UG199 (v1.2) Apr il 19, 2008 P ower Regulat ion R The FPGA can drive VMARGIN_DN_xxxx_N and VMARGIN_UP_xxxx_N signals, where xxxx indicates one of the six main power regulators: SSTL2, HS TL, SSTL18, VCC1V0, VCC2V5, and VCC3V3.
36 www .xilinx.com Vir tex-5 FPGA ML5 61 User Gu ide UG199 (v1.2) April 19, 2008 Chapter 3: Har dware De scription R Ta b l e 3 - 1 8 summarizes the inhibit headers.
Virtex-5 FPGA ML561 User Guide www .xilinx.com 37 UG199 (v1.2) Apr il 19, 2008 Board Design Considerations R For W rite data and terminations at the memory , if the trace length from the r eceiver pin to the termination resistor can be guaranteed to be within 0.
38 www .xilinx.com Vir tex-5 FPGA ML5 61 User Gu ide UG199 (v1.2) April 19, 2008 Chapter 3: Har dware De scription R Ta b l e 3 - 1 9 shows the details of the dielectric mate rial and constr uction for each layer and the contro lled impedance values for the signal layers.
Virtex-5 FPGA ML561 User Guide www .xilinx.com 39 UG199 (v1.2) Apr il 19, 2008 R Chapter 4 Electrical Requir ements This chapter provides the electrical re quirements for the V irtex -5 FPGA ML561 Development Board .
40 www .xilinx.com Vir tex-5 FPGA ML5 61 User Gu ide UG199 (v1.2) April 19, 2008 Chapter 4: Electrical Requ irements R T able 4-1: ML561 P ower Consumption Device Description Quantity V olta g e (V) Current (mA) Pow e r (W) Sour ce T otal A vailable P ower 5V Power Supply 1 5.
Virtex-5 FPGA ML561 User Guide www .xilinx.com 41 UG199 (v1.2) Apr il 19, 2008 P ower Consumptio n R P ower Modules Capacity V CCINT Power Plane (1.0V) 1 1.00 15000 15.0 T I PTH05010 15A Module Da ta Sheet HSTL FPGA Power Plane (1.8V) 1 1.80 15000 27.
42 www .xilinx.com Vir tex-5 FPGA ML5 61 User Gu ide UG199 (v1.2) April 19, 2008 Chapter 4: Electrical Requ irements R Ta b l e 4 - 2 lists the 12 differe nt power planes on the V irtex-5 FPGA ML 561 Development Board.
Virtex-5 FPGA ML561 User Guide www .xilinx.com 43 UG199 (v1.2) Apr il 19, 2008 P ower Consumptio n R current can support a voltage swing of up to (16 mA * 50 Ω ) = 800 mV , which is s uf ficient to meet the output voltage spec ification s for SSTL18, SSTL2, and HSTL18 I/O standar ds.
44 www .xilinx.com Vir tex-5 FPGA ML5 61 User Gu ide UG199 (v1.2) April 19, 2008 Chapter 4: Electrical Requ irements R SSTL18 FPGA Power Plane (1.8V) Capacity 1 1.8 15000 27.0 17.5 TI PTH05010 15A Module Data Sheet DDR2 x16 Memory 2 1.8 250 0.9 Micron DDR2 Com ponent Data Sheet DDR2 DIMM 2 1.
Virtex-5 FPGA ML561 User Guide www .xilinx.com 45 UG199 (v1.2) Apr il 19, 2008 P ower Consumptio n R System ACE Controller 1 3.3 200 0.7 DS080 , System ACE CompactFlash Solution 33 MHz Oscillator 2 3.3 45 0.3 Epson SG-8002CA Data Sheet 3.3V Power Plane Capacity 1 3.
46 www .xilinx.com Vir tex-5 FPGA ML5 61 User Gu ide UG199 (v1.2) April 19, 2008 Chapter 4: Electrical Requ irements R FPGA Internal P o wer Budget Ta b l e 4 - 4 summarizes power consumption estimates by each of the three XC5VLX50T-FFG1 136 FPGA s on the V irtex-5 FPGA ML56 1 Development Board.
Virtex-5 FPGA ML561 User Guide www .xilinx.com 47 UG199 (v1.2) Apr il 19, 2008 R Chapter 5 Signal Integrity Recommendations T ermination and T ransmission Line Summaries The following are common r eco.
48 www .xilinx.com Vir tex-5 FPGA ML5 61 User Gu ide UG199 (v1.2) April 19, 2008 Chapter 5: Signal Integrity Recommendatio ns R T able 5-1: DDR400 SDRAM Component T erminations Signal FPGA Driver T ermination at FPGA T ermination at Memory Data (DQ) SSTL2_II_DCI No termination 50 Ω pull-up to 1.
Virtex-5 FPGA ML561 User Guide www .xilinx.com 49 UG199 (v1.2) Apr il 19, 2008 T ermination and T ransmission Line Summaries R T able 5-4: QDRII SRAM T erminat ions Signal FPGA Driver T ermination at FPGA T ermination at Memory W rite Data (D) HSTL_I_18 No termination 50 Ω pull-up to 0.
50 www .xilinx.com Vir tex-5 FPGA ML5 61 User Gu ide UG199 (v1.2) April 19, 2008 Chapter 5: Signal Integrity Recommendatio ns R.
Virtex-5 FPGA ML561 User Guide www .xilinx.com 51 UG199 (v1.2) Apr il 19, 2008 R Chapter 6 Configuration This chapter provides a brief description of th e FPGA configuration methods used on the V irtex-5 FPGA ML561 Development Board.
52 www .xilinx.com Vir tex-5 FPGA ML5 61 User Gu ide UG199 (v1.2) April 19, 2008 Chapter 6: Configuration R JT A G Chain Four devices (the Syst em ACE chip and th ree XC5VLX50T -FFG1 136 FPGAs) are connected via a JT AG chain on the V irtex-5 FPGA ML561 Development Boar d.
Virtex-5 FPGA ML561 User Guide www .xilinx.com 53 UG199 (v1.2) Apr il 19, 2008 System A CE Interf ace R Ta b l e 6 - 2 shows the System ACE interface signal names, descriptions, and pin assignments .
54 www .xilinx.com Vir tex-5 FPGA ML5 61 User Gu ide UG199 (v1.2) April 19, 2008 Chapter 6: Configuration R.
Virtex-5 FPGA ML561 User Guide www .xilinx.com 55 UG199 (v1.2) Apr il 19, 2008 R Chapter 7 ML561 Hardwar e-Simulation Corr elation This chapter contains the following sections: • “Introduction” .
56 www .xilinx.com Vir tex-5 FPGA ML5 61 User Gu ide UG199 (v1.2) April 19, 2008 Chapter 7: ML561 Har dware-Sim ulation Correlation R illustrated here for these s ignals can be easily adopted to perform SI analysis for any other memory interface signal on the ML561 boar d.
Virtex-5 FPGA ML561 User Guide www .xilinx.com 57 UG199 (v1.2) Apr il 19, 2008 T est Setup R strobe, a random value can be applied to data bits from one cycle to anoth er . A 63-bit PRBS6 (1) (PRBS of or der 6) test pattern stimulus is used for this analysis.
58 www .xilinx.com Vir tex-5 FPGA ML5 61 User Gu ide UG199 (v1.2) April 19, 2008 Chapter 7: ML561 Har dware-Sim ulation Correlation R ♦ DDR2 mask (for nominal VDDQ = 1.8V and VREF = 0.9V): - VIH(ac)-min = VREF + 200 mV = 1.1V - VIH(dc)-min = VREF + 125 mV = 1.
Virtex-5 FPGA ML561 User Guide www .xilinx.com 59 UG199 (v1.2) Apr il 19, 2008 Signal Integrity Correlatio n Results R DDR2 Component Write Operation This subsection shows the test r esults for the DDR2_DQ_BY2_B3 signal from FPGA1 (U7) to the DDR2 memory component (U12) measure d at 333 MHz (667 Mb/s), where the unit interval (UI) = 1.
60 www .xilinx.com Vir tex-5 FPGA ML5 61 User Gu ide UG199 (v1.2) April 19, 2008 Chapter 7: ML561 Har dware-Sim ulation Correlation R DDR2 DQ is a bidirectional signal.
Virtex-5 FPGA ML561 User Guide www .xilinx.com 61 UG199 (v1.2) Apr il 19, 2008 Signal Integrity Correlatio n Results R Figure 7- 4: DDR2 Component Write HW Measurement - Eye Scope Shot at Probe P oint (DDR2 Memory Via) UG199_c7_04_071107 Figure 7- 5: DDR2 Component Write Correlation - Ey e Scope Shot at Probe P oint (Slo w Corner) 0.
62 www .xilinx.com Vir tex-5 FPGA ML5 61 User Gu ide UG199 (v1.2) April 19, 2008 Chapter 7: ML561 Har dware-Sim ulation Correlation R Figure 7-6: DDR2 Component Write HW Measurement - W avef orm Scope.
Virtex-5 FPGA ML561 User Guide www .xilinx.com 63 UG199 (v1.2) Apr il 19, 2008 Signal Integrity Correlatio n Results R Figure 7- 8: DDR2 Component Write Extrapolation - Ey e Scope Shot at Receiver IOB (Slow Co rner) -200.0 200.0 600.0 Time (ps) Voltage (mV) 1000.
64 www .xilinx.com Vir tex-5 FPGA ML5 61 User Gu ide UG199 (v1.2) April 19, 2008 Chapter 7: ML561 Har dware-Sim ulation Correlation R Figure 7-10: DDR2 Component Write Extrapolatio n - Eye Scope Shot at Rece iver IOB (Fast Corner) UG199_c7_10_071007 -100.
Virtex-5 FPGA ML561 User Guide www .xilinx.com 65 UG199 (v1.2) Apr il 19, 2008 Signal Integrity Correlatio n Results R DDR2 Component Read Operation This subsection shows the test re sults fo r the DDR2_DQ_BY2_B3 signal fr om the DDR2 memory component (U12) to FPGA1 (U7) me asured at 333 MHz (667 Mb/s), wher e the unit interval (UI) = 1.
66 www .xilinx.com Vir tex-5 FPGA ML5 61 User Gu ide UG199 (v1.2) April 19, 2008 Chapter 7: ML561 Har dware-Sim ulation Correlation R Figure 7-13: DDR2 Component Read HW Measurement - Eye Scope Shot at Pr obe Po int (FPGA1 Via) UG199_c7_13_071107 Figure 7-14 : DDR2 Component Read Correlation - Eye Scope Shot at Pr obe P oint (Slo w Corner) 800.
Virtex-5 FPGA ML561 User Guide www .xilinx.com 67 UG199 (v1.2) Apr il 19, 2008 Signal Integrity Correlatio n Results R Figure 7-15 : DDR2 Component Read HW Measurement - W avef orm Scope Shot at Probe P oint (FPGA1 Via) UG199_c7_15_071107 Figure 7-16: DDR2 Component Read Corre lation - W avef orm Scope Shot at Pr obe P oint (Slow Corner) 65.
68 www .xilinx.com Vir tex-5 FPGA ML5 61 User Gu ide UG199 (v1.2) April 19, 2008 Chapter 7: ML561 Har dware-Sim ulation Correlation R Figure 7-17: DDR2 Component Read Extrap olation - Eye Scope Shot at Receiver IOB ( Slow Corner) 800.0 1200.0 1600.0 2000.
Virtex-5 FPGA ML561 User Guide www .xilinx.com 69 UG199 (v1.2) Apr il 19, 2008 Signal Integrity Correlatio n Results R Figure 7-19: DDR2 Component Read Extr apolation - Eye Scope Shot at Rece iver IOB (Fast Corner) 800.0 1200.0 1600.0 2000.0 2400.0 2800.
70 www .xilinx.com Vir tex-5 FPGA ML5 61 User Gu ide UG199 (v1.2) April 19, 2008 Chapter 7: ML561 Har dware-Sim ulation Correlation R DDR2 DIMM Write Operation This subsection shows the test re sults for the DDR2_DIMM_DQ_BY2_B3 signal fr om FPGA2 (U5) to the DDR2 DIMM (XP2) measured at 333 MHz (667 Mb/s), wher e the unit interval (UI) = 1.
Virtex-5 FPGA ML561 User Guide www .xilinx.com 71 UG199 (v1.2) Apr il 19, 2008 Signal Integrity Correlatio n Results R DDR2 DQ is a bidirectional signal.
72 www .xilinx.com Vir tex-5 FPGA ML5 61 User Gu ide UG199 (v1.2) April 19, 2008 Chapter 7: ML561 Har dware-Sim ulation Correlation R Figure 7- 22: DDR2 D IMM Write HW Measurement - Eye Scope Sh ot at.
Virtex-5 FPGA ML561 User Guide www .xilinx.com 73 UG199 (v1.2) Apr il 19, 2008 Signal Integrity Correlatio n Results R Figure 7-24: DDR2 DIMM Write HW Measur ement - W avef orm Scope Shot at Pr obe P oint #1 (DDR2 Memory Via) UG199_c7_24_071107 Figure 7-25: DDR2 DIMM Write Correlation - W avef orm Scope Shot at Probe P oint #1 (Slow Corner) 95.
74 www .xilinx.com Vir tex-5 FPGA ML5 61 User Gu ide UG199 (v1.2) April 19, 2008 Chapter 7: ML561 Har dware-Sim ulation Correlation R Figure 7-26: DDR2 DIMM Write Extrapolation - Eye Scope Shot at Receiver IOB (S low Corner) 1000.0 1400.0 1800.0 2200.
Virtex-5 FPGA ML561 User Guide www .xilinx.com 75 UG199 (v1.2) Apr il 19, 2008 Signal Integrity Correlatio n Results R Figure 7- 28: DDR2 D IMM Write Extrapolation - Eye Scop e Shot at Receiver IOB (F ast C orner) 400.0 800.0 1200.0 1600.0 2000.0 2400.
76 www .xilinx.com Vir tex-5 FPGA ML5 61 User Gu ide UG199 (v1.2) April 19, 2008 Chapter 7: ML561 Har dware-Sim ulation Correlation R DDR2 DIMM Read Operation This subsection shows the test re sults fo r the DDR2_DIMM_DQ_BY2_B3 s ignal from the DDR2 DIMM (XP2) to FPGA2 (U5) measured at 333 MHz (667 Mb/s), wher e the unit interval (UI) = 1.
Virtex-5 FPGA ML561 User Guide www .xilinx.com 77 UG199 (v1.2) Apr il 19, 2008 Signal Integrity Correlatio n Results R Figure 7- 31: DDR2 DIMM Read HW Measurement - Eye Sc ope Shot at Probe P oint (FPGA1 Via) UG199_c7_31_071107 Figure 7- 32: DDR2 DIMM Read Correlation - Ey e Scope Shot at Pr obe P oint (Slow Co rner) 2000.
78 www .xilinx.com Vir tex-5 FPGA ML5 61 User Gu ide UG199 (v1.2) April 19, 2008 Chapter 7: ML561 Har dware-Sim ulation Correlation R Figure 7-33: DDR2 DIMM Read HW Measurement - Wa veform Scope Shot at Probe P oint (FPGA1 Via) UG199_c7_33_071107 Figure 7- 34: DDR2 D IMM Read Correlation - W avef orm Scop e Shot at Probe P oint (Slow Corner) 25.
Virtex-5 FPGA ML561 User Guide www .xilinx.com 79 UG199 (v1.2) Apr il 19, 2008 Signal Integrity Correlatio n Results R Figure 7- 35: DDR2 D IMM Read Extrapolation - Eye Scop e Shot at Receiver IOB (Slow Corner) 2000.0 2400.0 2800.0 3200.0 3600.0 4000.
80 www .xilinx.com Vir tex-5 FPGA ML5 61 User Gu ide UG199 (v1.2) April 19, 2008 Chapter 7: ML561 Har dware-Sim ulation Correlation R Figure 7-37: DDR2 DIMM Read Extrapolat ion - Eye Scope Shot at Receiver IOB (F ast Corner) 400.0 800.0 1200.0 1600.0 2000.
Virtex-5 FPGA ML561 User Guide www .xilinx.com 81 UG199 (v1.2) Apr il 19, 2008 Signal Integrity Correlatio n Results R QDRII Write Operation This subsection shows the test re sults for the QDR2_D_BY0_B5 signal from FPGA3 (U34) to QDRII memory (U35) measured at 300 M Hz (600 Mb/s), where the unit interval (UI) = 167 ns.
82 www .xilinx.com Vir tex-5 FPGA ML5 61 User Gu ide UG199 (v1.2) April 19, 2008 Chapter 7: ML561 Har dware-Sim ulation Correlation R Figure 7- 40: QDRII Write HW Measurement - Eye Scope Shot at Pr obe P o int (QDRII Memory Via) UG199_c7_40_071107 Figure 7-41: QDRII Write C orrelation - Eye Scope Shot at Probe P oint (Slow Corner) 0.
Virtex-5 FPGA ML561 User Guide www .xilinx.com 83 UG199 (v1.2) Apr il 19, 2008 Signal Integrity Correlatio n Results R Figure 7- 42: QD RII Write HW Measurement - W aveform Scope Shot at Pr obe P oint (Q DRII Memory Via) UG199_c7_42_071107 Figure 7-43: QDRII Write Correla tion - W aveform Scope Shot at Probe P oint (S low Corner) 110.
84 www .xilinx.com Vir tex-5 FPGA ML5 61 User Gu ide UG199 (v1.2) April 19, 2008 Chapter 7: ML561 Har dware-Sim ulation Correlation R Figure 7-44: QDRII Write Extrapola tion - Eye Scope Shot at Receiver IO B (Slow Corner) 0.000 400.0 800.0 1200.0 1600.
Virtex-5 FPGA ML561 User Guide www .xilinx.com 85 UG199 (v1.2) Apr il 19, 2008 Signal Integrity Correlatio n Results R Figure 7- 46: QDRII Write Extrapolation - Eye Scope Shot at Receiver IOB (F ast Corner) 800.0 1200.0 1600.0 2000.0 2400.0 2800.0 -1900.
86 www .xilinx.com Vir tex-5 FPGA ML5 61 User Gu ide UG199 (v1.2) April 19, 2008 Chapter 7: ML561 Har dware-Sim ulation Correlation R QDRII Read Operation This subsection shows the test re sults for the QDR2_Q_BY0_B5 signal from QDRII memory (U35) to FPGA 3 (U34) measur ed at 300 MHz (600 Mb/s), wher e the unit int erval (UI) = 1.
Virtex-5 FPGA ML561 User Guide www .xilinx.com 87 UG199 (v1.2) Apr il 19, 2008 Signal Integrity Correlatio n Results R Figure 7-49: QDRII Read HW M easurement - Eye Diagram Scope Shot at Probe P oint (FPGA3 Via) UG199_c7_49_071107 Figure 7-50: QDRII Read Corr elation - Ey e Diagram Scope Sho t at Pr obe P oint (Slo w Corner) 800.
88 www .xilinx.com Vir tex-5 FPGA ML5 61 User Gu ide UG199 (v1.2) April 19, 2008 Chapter 7: ML561 Har dware-Sim ulation Correlation R Figure 7-51 : QDRII Read HW Measurement - W a veform Sc ope Shot at Pr obe P oint (FPGA3 Via) UG199_c7_51_071107 Figure 7-52: QDRII Read Correlation - W avef orm Scope Shot at Probe P oint (Slow Corne r) 20.
Virtex-5 FPGA ML561 User Guide www .xilinx.com 89 UG199 (v1.2) Apr il 19, 2008 Signal Integrity Correlatio n Results R Figure 7-53: QDRII Read Extra polation - Eye Scope Shot at Re ceiver IOB (Slow Corner) 1000.0 1400.0 1800.0 2200.0 2600.0 -200.0 0.000 200.
90 www .xilinx.com Vir tex-5 FPGA ML5 61 User Gu ide UG199 (v1.2) April 19, 2008 Chapter 7: ML561 Har dware-Sim ulation Correlation R Figure 7- 55: QDRII Read Extrapolation - Ey e Scope Shot at Receiver IOB (F ast Corner) 1200.0 1600.0 2000.0 2400.0 2800.
Virtex-5 FPGA ML561 User Guide www .xilinx.com 91 UG199 (v1.2) Apr il 19, 2008 Summary and Recommendations R Summary and Recommendations The first objective of this exer cise is to establish correlation between hard ware measurements and the simulation at the pr ob e point.
92 www .xilinx.com Vir tex-5 FPGA ML5 61 User Gu ide UG199 (v1.2) April 19, 2008 Chapter 7: ML561 Har dware-Sim ulation Correlation R Ta b l e 7 - 1 6 summarizes the extrapolated SI char acteristics of al l six test signals.
Virtex-5 FPGA ML561 User Guide www .xilinx.com 93 UG199 (v1.2) Apr il 19, 2008 How to Generate a Us er-Specific FPGA IBIS Model R How to Generate a User -Specific FPGA IBIS Model The following steps indicate how to generate an IBIS model: 1. Under ISE, open your fully compiled pr oject.
94 www .xilinx.com Vir tex-5 FPGA ML5 61 User Gu ide UG199 (v1.2) April 19, 2008 Chapter 7: ML561 Har dware-Sim ulation Correlation R.
Virtex-5 FPGA ML561 User Guide www .xilinx.com 95 UG199 (v1.2) Apr il 19, 2008 R Appendix A FPGA Pinouts This appendix provides the pinouts for th e thr ee FPGAs on the V irtex-5 FPGA ML561 Development Boar d. The toolkit CD shipped with every ML561 contains sample UCFs for each memory interface.
96 www .xilinx.com Vir tex-5 FPGA ML5 61 User Gu ide UG199 (v1.2) April 19, 2008 Appendix A: FPGA Pinouts R DDR400 Component Interface (cont.) DDR1_DQ_BY0_B4 AM32 DDR1_DQ_ BY2_B4 R32 DDR1_DQ_BY0_B5 AM.
Virtex-5 FPGA ML561 User Guide www .xilinx.com 97 UG199 (v1.2) Apr il 19, 2008 FPGA #1 Pinout R DDR2 Component Interface (cont.) DDR2_WE_N J21 DDR2_DQ_BY2_B2 N25 DDR2_DM_BY0 U30 DDR2_DQ_BY2_B3 P25 DDR.
98 www .xilinx.com Vir tex-5 FPGA ML5 61 User Gu ide UG199 (v1.2) April 19, 2008 Appendix A: FPGA Pinouts R FPGA #1 MII Link Interface FPGA2_TO_FPGA1_MII_TX_CLK J10 FPGA3_TO_FPGA1_MII_TX_CLK D10 FPGA2.
Virtex-5 FPGA ML561 User Guide www .xilinx.com 99 UG199 (v1.2) Apr il 19, 2008 FPGA #1 Pinout R FPGA #1 T est Display Signals FPGA1_7SEG_0_N AG17 FPGA1_7SEG_6_N AF19 FPGA1_7SEG_1_N AH18 FPGA1_7SEG_DP_.
100 www .xilinx.com Vir tex-5 FPGA ML5 61 User Gu ide UG199 (v1.2) April 19, 2008 Appendix A: FPGA Pinouts R FPGA #2 Pinout Ta b l e A - 2 lists the connections for FPGA #2 (U5).
Virtex-5 FPGA ML561 User Guide www .xilinx.com 101 UG199 (v1.2) Apr il 19, 2008 FPGA #2 Pinout R DDR2 DIMM Deep Interface (cont.) DDR2_DIMM3_CK2_P AA25 D DR2_DIMM_DQ_BY0_B4 R27 DDR2_DIMM3_CKE0 AE28 DD.
102 www .xilinx.com Vir tex-5 FPGA ML5 61 User Gu ide UG199 (v1.2) April 19, 2008 Appendix A: FPGA Pinouts R DDR2 DIMM Deep Interface (cont.) DDR2_DIMM_DQ_BY4_B4 V34 DDR2_DIMM_DQ_BY7_B7 Y32 DDR2_DIMM_.
Virtex-5 FPGA ML561 User Guide www .xilinx.com 103 UG199 (v1.2) Apr il 19, 2008 FPGA #2 Pinout R DDR2 DIMM Wide Interface (cont.) DDR2_DIMM5_CS0_N V24 DDR2_DIMM_DQ_BY1 1_B5 G6 DDR2_DIMM5_CS1_N W24 DDR.
104 www .xilinx.com Vir tex-5 FPGA ML5 61 User Gu ide UG199 (v1.2) April 19, 2008 Appendix A: FPGA Pinouts R DDR2 DIMM Wide Interface (cont.) DDR2_DIMM_DQ_BY15_B5 AD5 DDR2_DIMM_DQ_CB8_15_B4 N7 DDR2_DI.
Virtex-5 FPGA ML561 User Guide www .xilinx.com 105 UG199 (v1.2) Apr il 19, 2008 FPGA #2 Pinout R DDR2 DIMM Miscellaneous Signals (cont.) DDR2_DIMM5_CNTL_P AR AB8 DDR2_DIMM2_SA2 N24 DDR2_DIMM5_CNTL_P A.
106 www .xilinx.com Vir tex-5 FPGA ML5 61 User Gu ide UG199 (v1.2) April 19, 2008 Appendix A: FPGA Pinouts R FPGA #2 T est and Deb ug Signals FPGA2_DIP0 AG18 FPGA2_SOFTTOUCH_BY1_B7 H17 FPGA2_DIP1 AG15.
Virtex-5 FPGA ML561 User Guide www .xilinx.com 107 UG199 (v1.2) Apr il 19, 2008 FPGA #2 Pinout R FPGA #2 External Interfaces (cont.) FPGA2_TXN0_BK120 B3 FPGA2_USB_CTS_N L15 FPGA2_TXN1_BK120 D2 FPGA2_U.
108 www .xilinx.com Vir tex-5 FPGA ML5 61 User Gu ide UG199 (v1.2) April 19, 2008 Appendix A: FPGA Pinouts R FPGA #3 Pinout Ta b l e A - 3 lists the connections for FPGA #3 (U34).
Virtex-5 FPGA ML561 User Guide www .xilinx.com 109 UG199 (v1.2) Apr il 19, 2008 FPGA #3 Pinout R QDRII Memory Interface (cont.) QDR2_D_BY0_B5 M31 QD R2_D_BY4_B1 AH29 QDR2_D_BY0_B6 P30 QD R2_D_BY4_B2 A.
110 www .xilinx.com Vir tex-5 FPGA ML5 61 User Gu ide UG199 (v1.2) April 19, 2008 Appendix A: FPGA Pinouts R QDRII Memory Interface (cont.) QDR2_D_BY7_B6 U28 QDR2_Q_BY3_B2 G27 QDR2_D_BY7_B7 U27 QDR2_Q.
Virtex-5 FPGA ML561 User Guide www .xilinx.com 111 UG199 (v1.2) Apr il 19, 2008 FPGA #3 Pinout R QDRII Memory Interface (cont.) QDR2_Q_BY6_B7 V33 QDR2_Q_BY7_B4 W 29 QDR2_Q_BY6_B8 V32 QDR2_Q_BY7 _B5 Y3.
112 www .xilinx.com Vir tex-5 FPGA ML5 61 User Gu ide UG199 (v1.2) April 19, 2008 Appendix A: FPGA Pinouts R RLDRAM II Memory Interface (cont.) RLD2_D_BY0_B5 F8 RLD2_DM_BY2_3_N T9 RLD2_D_BY0_B6 F9 R L.
Virtex-5 FPGA ML561 User Guide www .xilinx.com 113 UG199 (v1.2) Apr il 19, 2008 FPGA #3 Pinout R RLDRAM II Memory Interface (cont.) RLD2_DQ_BY3_B4 M7 RLD2_DQ_BY3_B7 M5 RLD2_DQ_BY3_B5 N7 RLD2_DQ_BY3_B8.
114 www .xilinx.com Vir tex-5 FPGA ML5 61 User Gu ide UG199 (v1.2) April 19, 2008 Appendix A: FPGA Pinouts R FPGA #3 T est and Debug Signals (cont.) FPGA3_TEST_HDR_BY1_B4 AC24 FPGA3_TEST_HDR_BY1_B6 AE.
Virtex-5 FPGA ML561 User Guide www .xilinx.com 115 UG199 (v1.2) Apr il 19, 2008 R Appendix B Bill of Materials This appendix lists the bill of materials (B OM) for many of the components used for the assembly of the V irtex- 5 FPGA ML561 Development Boar d, Revision A.
116 www .xilinx.com Vir tex-5 FPGA ML5 61 User Gu ide UG199 (v1.2) April 19, 2008 Appendix B: Bill of Materials R Power 15A Power Module T exas Instrumen ts PTH05010-W AZ VR1, VR6, VR9 , VR10, VR12, VR 13 6A Power Module T exas Instruments PTH05000-W AZ VR2, VR4, VR1 4 4A LDO Maxim MAX8556ETE VR3, VR5, VR7, VR8 1.
Virtex-5 FPGA ML561 User Guide www .xilinx.com 117 UG199 (v1.2) Apr il 19, 2008 R Switch DIP (T est Inputs) ITT_INDUSTRIES SDA04H1KD SW1, SW2, SW6 System Reset (Black) Panasonic EVQ 1 1L07K SW4 Config.
118 www .xilinx.com Vir tex-5 FPGA ML5 61 User Gu ide UG199 (v1.2) April 19, 2008 Appendix B: Bill of Materials R.
Virtex-5 FPGA ML561 User Guide www .xilinx.com 119 UG199 (v1.2) Apr il 19, 2008 R Appendix C LCD Interface This appendix describes the LCD interface for the V irtex-5 FPGA ML 561 Development Board. General The V irtex-5 FPGA ML561 Development Boar d has a full graphical LCD panel.
120 www .xilinx.com Vir tex-5 FPGA ML5 61 User Gu ide UG199 (v1.2) April 19, 2008 Appendix C: LCD Interface R Ta b l e C - 1 summarizes the controller specificati ons. The on-chip RAM size is 65 x 132 = 8580 bits. Har dware Sc hematic Diagram Figure C-1 illustra tes the schematic for the display .
Virtex-5 FPGA ML561 User Guide www .xilinx.com 121 UG199 (v1.2) Apr il 19, 2008 Hardware Schematic Diagram R P eripheral De vice KS071 3 Figure C-2 is a block dia gram of the Samsung KS0713.
122 www .xilinx.com Vir tex-5 FPGA ML5 61 User Gu ide UG199 (v1.2) April 19, 2008 Appendix C: LCD Interface R Figure C-3 shows only the signals of interest for the LCD contr oller . The data sheet fr om the Samsung web pages provides a complete signal list ing.
Virtex-5 FPGA ML561 User Guide www .xilinx.com 123 UG199 (v1.2) Apr il 19, 2008 Hardware Schematic Diagram R Controller – Operation The pixels for the LCD panel ar e stored in the contr oller data RAM. This RAM is a 65-row by 132-column array . Each display pixel is represented by a single bit in the RAM array .
124 www .xilinx.com Vir tex-5 FPGA ML5 61 User Gu ide UG199 (v1.2) April 19, 2008 Appendix C: LCD Interface R 0010 DB0 Page 2 10H DB1 11 H DB2 12H DB3 13H DB4 14H DB5 15H DB6 16H DB7 17H 0011 DB0 Page.
Virtex-5 FPGA ML561 User Guide www .xilinx.com 125 UG199 (v1.2) Apr il 19, 2008 Hardware Schematic Diagram R When a page is address ed, all the bits repr es enting dots on the LCD panel can be accessed in that page. An array of 8x132 bits is availabl e.
126 www .xilinx.com Vir tex-5 FPGA ML5 61 User Gu ide UG199 (v1.2) April 19, 2008 Appendix C: LCD Interface R Controller – P o wer Supply Circuits Figure C-5 shows the power supply cir cuits. The po wer supply is used in the five times boost mode, where VDD is 3.
Virtex-5 FPGA ML561 User Guide www .xilinx.com 127 UG199 (v1.2) Apr il 19, 2008 Hardware Schematic Diagram R The voltage and contrast settings must be co nfigur ed befor e the LCD panel is r eady for operation. Figure C-6 s hows the initializati on procedur e require d to set up the LCD controller .
128 www .xilinx.com Vir tex-5 FPGA ML5 61 User Gu ide UG199 (v1.2) April 19, 2008 Appendix C: LCD Interface R • The voltage follower and voltage regulator are set to: ♦ Five times boost mode ♦ The V4, V3, V2, V1 , and V0 outputs de pend on the bias set tings of 1/9 or 1/7.
Virtex-5 FPGA ML561 User Guide www .xilinx.com 129 UG199 (v1.2) Apr il 19, 2008 Hardware Schematic Diagram R After the SHL bit is configur ed, these settings normally ar e not changed. • Select the LCD bias settin gs. ♦ The duty cycle is selected as 1/65 by ha r dwiring the controller IC pads on the display P CB.
130 www .xilinx.com Vir tex-5 FPGA ML5 61 User Gu ide UG199 (v1.2) April 19, 2008 Appendix C: LCD Interface R Instruction Set Ta b l e C - 6 shows the instruction set for the LCD panel.
Virtex-5 FPGA ML561 User Guide www .xilinx.com 131 UG199 (v1.2) Apr il 19, 2008 Hardware Schematic Diagram R Set page addr ess 0 0 1 0 1 1 P3 P2 P1 P0 This instruction s ets the address of the display data page. A ny RA M data bit can be accessed whe n its page address an d column a ddr ess ar e specified.
132 www .xilinx.com Vir tex-5 FPGA ML5 61 User Gu ide UG199 (v1.2) April 19, 2008 Appendix C: LCD Interface R R e v e r s e d i s p l a y O N / O F F 0 0 1010011 R E V REV RAM bit data = '1'.
Virtex-5 FPGA ML561 User Guide www .xilinx.com 133 UG199 (v1.2) Apr il 19, 2008 Hardware Schematic Diagram R Read/Write Character istics (6800 Mode) Ta b l e C - 7 list the read and wr ite timing para meters in 6800 mode. The associated waveforms for these parameters are illustrated in Figur e C-7 .
134 www .xilinx.com Vir tex-5 FPGA ML5 61 User Gu ide UG199 (v1.2) April 19, 2008 Appendix C: LCD Interface R Design Examples LCD P anel Used in Full Graphics Mode The LCD controller RAM has eight 132-byte page s (in fact, there ar e nine pages; page 9 is special).
Virtex-5 FPGA ML561 User Guide www .xilinx.com 135 UG199 (v1.2) Apr il 19, 2008 Hardware Schematic Diagram R LCD P anel Used in Character Mode This design example r equir es a byte r epr esen ting a command or data to be displayed as input. • When the Enable signal is Low , nothing happens.
136 www .xilinx.com Vir tex-5 FPGA ML5 61 User Gu ide UG199 (v1.2) April 19, 2008 Appendix C: LCD Interface R Displa y Data Byte The supplied byte must be a valid ASCII repr esentation of a character as shown in Figure C-9 . The character set is stored in block RAM (used as ROM).
Virtex-5 FPGA ML561 User Guide www .xilinx.com 137 UG199 (v1.2) Apr il 19, 2008 Hardware Schematic Diagram R When presenting byte va lue 30 hex, character 0 must be displayed. Shifting the value 001 10000b (30h) up three positions gives the value 180h or 348d.
138 www .xilinx.com Vir tex-5 FPGA ML5 61 User Gu ide UG199 (v1.2) April 19, 2008 Appendix C: LCD Interface R Figure C-1 1 shows a block diagram of the LCD char acter generator controller . Character data is latched and then shifted left three positi ons.
Virtex-5 FPGA ML561 User Guide www .xilinx.com 139 UG199 (v1.2) Apr il 19, 2008 Hardware Schematic Diagram R Arra y Connector Numbering Figure C-12 shows the LCD connections for Bank 0.
140 www .xilinx.com Vir tex-5 FPGA ML5 61 User Gu ide UG199 (v1.2) April 19, 2008 Appendix C: LCD Interface R.
Een belangrijk punt na aankoop van elk apparaat Xilinx ML561 (of zelfs voordat je het koopt) is om de handleiding te lezen. Dit moeten wij doen vanwege een paar simpele redenen:
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