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User Guide [optional] UG534 (v1.2.1 ) January 21, 20 10 [option al] ML605 Har d ware User Guide UG534 (v1.2.1 ) January 21, 20 10.
ML605 Hardware User Guide www .xilinx.com UG534 (v1.2.1) January 21, 2010 Xilinx is disclosing this user gui de, manual, rel ease note, and/or sp ecification (the "Documentation") to y ou solely f or use in the de velopment of designs to operate with Xilinx hardw are de vices.
ML605 Hardware User Guide www .xilinx.com 3 UG534 (v1.2.1) January 21, 2010 Preface: About This Guide Guide Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Additional Documentation .
4 www .xilinx.com ML6 05 Hard ware User Guid e UG534 (v1.2.1) January 21 , 2010 FPGA_PROG_B Pushbutton SW4 (Active-Low) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 SYSACE_RESET_B Pu shbutton SW3 (Active-Low) . . . . . . . . . . . .
ML605 Hardware User Guide www .xilinx.com 5 UG534 (v1.2.1) January 21, 2010 Pr eface About This Guide This manual accompan ies the V irtex®-6 FPGA M L605 Evaluation Boa rd and contains information about the ML605 hardwar e and software tools.
6 www .xilinx.com ML6 05 Hard ware User Guid e UG534 (v1.2.1) January 21 , 2010 Pref ace: About This Guide • V irtex-6 FPGA Memory Resource s User Guide The functionality of the b lock RAM and FIFO are described in this u ser guide.
ML605 Hardware User Guide www .xilinx.com 7 UG534 (v1.2.1) January 21, 2010 Chapter 1 ML605 Evaluation Board Overview The ML605 boar d enables har dwar e and softwar e developers to cr eate or evaluat e designs targeting the V irtex®-6 XC6VLX240T -1FFG1 156 FPGA.
8 www .xilinx.com ML6 05 Hard ware User Guid e UG534 (v1.2.1) January 21 , 2010 Chapter 1: ML605 Ev aluation Board F eatures The ML605 provides the following featur es: • 1. V irtex-6 XC 6VLX240T -1 FFG1 156 FPGA • 2. 512 MB DDR3 Memory SODIMM • 3.
ML605 Hardware User Guide www .xilinx.com 9 UG534 (v1.2.1) January 21, 2010 Overvie w • 16. Status LEDs ♦ Ethernet status ♦ FPGA INIT ♦ FPGA DONE ♦ System ACE CF Status • 17.
10 www .xilinx.com ML6 05 Hard ware User Guid e UG534 (v1.2.1) January 21 , 2010 Chapter 1: ML605 Ev aluation Board Bloc k Diagra m Figur e 1- 1 shows a high-level block diagram of the ML605 and its peripherals. Related Xilinx Documents Prior to using the ML605 Evaluation Board, user s should be famil iar with Xilinx re sources.
ML605 Hardware User Guide www .xilinx.com 11 UG534 (v1.2.1) January 21, 2010 Detailed Des cription Detailed Description Figur e 1-2 shows a board photo with numbered featur es corresponding to Ta b l e 1 - 1 and the section headings in this document.
12 www .xilinx.com ML6 05 Hard ware User Guid e UG534 (v1.2.1) January 21 , 2010 Chapter 1: ML605 Ev aluation Board 7 Clock generation 200 MHz OSC, oscillator socket, SMA connectors 30 a. 200 MHz oscillator (on backside) Epson 200 MHz 2.5V L VDS OSC 30 b.
ML605 Hardware User Guide www .xilinx.com 13 UG534 (v1.2.1) January 21, 2010 Detailed Des cription 1. Vir te x-6 XC6VLX 240T -1FFG1156 FPGA A V irtex-6 XC6V LX240T -1FFG1 156 FPGA is installed on the embedded development board.
14 www .xilinx.com ML6 05 Hard ware User Guid e UG534 (v1.2.1) January 21 , 2010 Chapter 1: ML605 Ev aluation Board The ML605 supports Mas ter BPI-Up, JT AG, an d Slave SelectMAP . These are selected by setting M[2:0] options 010 , 101 and 110 shown in Ta b l e 1 - 2 .
ML605 Hardware User Guide www .xilinx.com 15 UG534 (v1.2.1) January 21, 2010 Detailed Des cription Ref erences See the Xilinx V irtex-6 FPG A docu mentation for more information at http://www .
16 www .xilinx.com ML6 05 Hard ware User Guid e UG534 (v1.2.1) January 21 , 2010 Chapter 1: ML605 Ev aluation Board A15 DDR3_A6 90 A6 B15 DDR3_A7 86 A7 G15 DDR3_A8 89 A8 F15 DDR3_A9 85 A9 M16 DDR3_A10.
ML605 Hardware User Guide www .xilinx.com 17 UG534 (v1.2.1) January 21, 2010 Detailed Des cription G12 DDR3_D20 40 DQ20 G13 DDR3_D21 42 DQ21 F14 DDR3_D22 50 DQ22 H14 DDR3_D23 52 DQ23 C19 DDR3_D24 57 D.
18 www .xilinx.com ML6 05 Hard ware User Guid e UG534 (v1.2.1) January 21 , 2010 Chapter 1: ML605 Ev aluation Board E24 DDR3_D54 174 DQ54 G25 DDR3_D55 176 DQ55 F28 DDR3_D56 181 DQ56 B31 DDR3_D57 183 D.
ML605 Hardware User Guide www .xilinx.com 19 UG534 (v1.2.1) January 21, 2010 Detailed Des cription The Memory Interface Generator (MIG) tool guidelines specify a set of U1 FPGA “No Connect” pins.
20 www .xilinx.com ML6 05 Hard ware User Guid e UG534 (v1.2.1) January 21 , 2010 Chapter 1: ML605 Ev aluation Board 3. 12 8 Mb Platf or m Flash XL A 128 Mb Xilinx XCF128X-FTG64C Platform Fl ash XL dev.
ML605 Hardware User Guide www .xilinx.com 21 UG534 (v1.2.1) January 21, 2010 Detailed Des cription ML605 Flash Boot Options The ML605 has two parallel wired fl ash memory devices as shown in Figur e 1-3 .
22 www .xilinx.com ML6 05 Hard ware User Guid e UG534 (v1.2.1) January 21 , 2010 Chapter 1: ML605 Ev aluation Board AF24 FLASH_D0 34 DQ0 F2 DQ00 AF25 FLASH_D1 36 DQ1 E2 DQ01 W24 FLASH_D2 39 DQ2 G3 DQ0.
ML605 Hardware User Guide www .xilinx.com 23 UG534 (v1.2.1) January 21, 2010 Detailed Des cription FPGA Design Considerations f or the Configuration Flash After FPGA configuration, the FPGA design can disable the configuration flash or access the configuration flash to r ead/write code or data.
24 www .xilinx.com ML6 05 Hard ware User Guid e UG534 (v1.2.1) January 21 , 2010 Chapter 1: ML605 Ev aluation Board 5. System A CE CF and CompactFlash Connector The Xilinx System ACE CompactFlash (CF) configuration controller allows a T ype I or T ype II CompactFlash ca rd to pr ogram the FPGA through the JT AG port.
ML605 Hardware User Guide www .xilinx.com 25 UG534 (v1.2.1) January 21, 2010 Detailed Des cription Ta b l e 1 - 6 list s the System ACE CF conne ctions. Ref erences See the System ACE CF product page and the System ACE CompactFlash Solu tion Data Sheet .
26 www .xilinx.com ML6 05 Hard ware User Guid e UG534 (v1.2.1) January 21 , 2010 Chapter 1: ML605 Ev aluation Board 6. USB JT A G JT AG configuration is pr ovided through on boar d USB-to-JT AG configuration logic wher e a computer host accesses the ML605 JT AG chai n through a T ype-A (computer host side) to T ype-Mini-B (ML605 side) USB cable.
ML605 Hardware User Guide www .xilinx.com 27 UG534 (v1.2.1) January 21, 2010 Detailed Des cription Th e J T A G c h a in c a n b e u s e d t o p ro g r a m t h e F P GA a n d a cc e s s t he F P G A f o r h a rdw a re a n d software debug.
28 www .xilinx.com ML6 05 Hard ware User Guid e UG534 (v1.2.1) January 21 , 2010 Chapter 1: ML605 Ev aluation Board X-Ref Target - Figure 1-7 Figure 1-7: ML605 Oscillator Soc ket Pin 1 Location Identi.
ML605 Hardware User Guide www .xilinx.com 29 UG534 (v1.2.1) January 21, 2010 Detailed Des cription SMA Connectors (Diff erential) A high-pr ecision clock signal can be provide d to the FPGA using dif fer ential clock signals through the onboar d 50-ohm SMA connectors J58(P)/J55(N).
30 www .xilinx.com ML6 05 Hard ware User Guid e UG534 (v1.2.1) January 21 , 2010 Chapter 1: ML605 Ev aluation Board GTX SMA Clock The ML605 includes a pair of SMA connector s for a GTX (MGT) Clock as described in Figur e 1-9 and Ta b l e 1 - 7 .
ML605 Hardware User Guide www .xilinx.com 31 UG534 (v1.2.1) January 21, 2010 Detailed Des cription 8 . Multi-Gigabit T ransceiv e rs (GTX MGTs) The ML605 provides access to 20 MGT s.
32 www .xilinx.com ML6 05 Hard ware User Guid e UG534 (v1.2.1) January 21 , 2010 Chapter 1: ML605 Ev aluation Board 9. PCI Express Endpoint Connectivity The 8-lane PCIe edge connector pe rforms data transfe rs at the rate of 2.5 GT/s for a Gen1 application and 5.
ML605 Hardware User Guide www .xilinx.com 33 UG534 (v1.2.1) January 21, 2010 Detailed Des cription Ta b l e 1 - 8 s h o w s t h e P C I e c o n ne c t o r ( P1 ) t h a t p r o vi d e s up t o 8 -l a n e ac c e s s t h r o u g h t he G T X transceivers to the V irtex-6 FPGA inte grated Endpoint block for PCIe designs.
34 www .xilinx.com ML6 05 Hard ware User Guid e UG534 (v1.2.1) January 21 , 2010 Chapter 1: ML605 Ev aluation Board The PCIe interface obtains its power from th e DC power s upply provided with the ML605 or thro ugh the 12V A TX power supply connector .
ML605 Hardware User Guide www .xilinx.com 35 UG534 (v1.2.1) January 21, 2010 Detailed Des cription Ref erences See the following websites for more V irtex-6 FPGA Integrated Endpoint Block for PCI Express inf ormation: • http://www .xilinx.com/pr oducts/ipcenter/V6_PCI_Express_Block.
36 www .xilinx.com ML6 05 Hard ware User Guid e UG534 (v1.2.1) January 21 , 2010 Chapter 1: ML605 Ev aluation Board 11. 10/100/1000 T r i-Speed Ether net PHY T h e M L 6 0 5 u t i l i z e s t h e o n b o a r d M a r v e l l A l a s k a P H Y d e v i c e ( 8 8 E 1111 ) f o r E t h e r n e t communications at 10, 100, or 1000 Mb/s.
ML605 Hardware User Guide www .xilinx.com 37 UG534 (v1.2.1) January 21, 2010 Detailed Des cription SGMII GTX T ransceiver Cloc k Generation An Integrated Circuit System s ICS844021I chip generates a high-quality , low-jitter , 125- MHz L VDS clock from an inexpensive 25-MHz crys tal oscillator .
38 www .xilinx.com ML6 05 Hard ware User Guid e UG534 (v1.2.1) January 21 , 2010 Chapter 1: ML605 Ev aluation Board Ref erences See the Marvell Alaska Gigabit Ethernet T ransceivers product page for more information. [Ref 28] Also, see the LogiCORE™ IP T ri-Mode Et hernet MAC User Guide .
ML605 Hardware User Guide www .xilinx.com 39 UG534 (v1.2.1) January 21, 2010 Detailed Des cription 12. USB-to-U AR T Bridge The ML605 contains a Silicon Labs CP2103G M USB-to-UAR T bridg e device (U34) whi ch allows connection to a host computer with a US B cable.
40 www .xilinx.com ML6 05 Hard ware User Guid e UG534 (v1.2.1) January 21 , 2010 Chapter 1: ML605 Ev aluation Board 13. USB Controller The ML605 provides USB support via a Cypr ess CY7C67300 EZ-Host™ Programmable Embedded USB Host and Peri pheral Contr olle r (U81).
ML605 Hardware User Guide www .xilinx.com 41 UG534 (v1.2.1) January 21, 2010 Detailed Des cription 14. D VI Codec The ML605 features a DVI connector (P3) to support an external video monitor . The DVI circuitry utilizes a Chr ontel CH7301C (U38) ca pable of 1600 X 1200 resolution with 24-bit color .
42 www .xilinx.com ML6 05 Hard ware User Guid e UG534 (v1.2.1) January 21 , 2010 Chapter 1: ML605 Ev aluation Board 15. IIC Bus The ML605 implements four IIC bus interfaces at the FPGA.
ML605 Hardware User Guide www .xilinx.com 43 UG534 (v1.2.1) January 21, 2010 Detailed Des cription X-Ref Target - Figure 1-14 Figure 1- 14: IIC Bus T opolog y U1 J6 3 P 3 U 3 8 BANK 3 4 IIC_ S D A_MAI.
44 www .xilinx.com ML6 05 Hard ware User Guid e UG534 (v1.2.1) January 21 , 2010 Chapter 1: ML605 Ev aluation Board 8 Kb NV Memory The ML605 hosts an 8 Kb ST Micr oelectr onics M24C08 -WDW6TP IIC parameter s torage memory device (U6) . The IIC addres s of U7 is 0b1010100, and U6 is not write protected (WP pin 7 is tied to GND).
ML605 Hardware User Guide www .xilinx.com 45 UG534 (v1.2.1) January 21, 2010 Detailed Des cription 16. Status LEDs Ta b l e 1 - 1 9 defines the status LEDs.
46 www .xilinx.com ML6 05 Hard ware User Guid e UG534 (v1.2.1) January 21 , 2010 Chapter 1: ML605 Ev aluation Board Ether net PHY Status LEDs The Ethernet PHY status LEDs ar e mounted to be visible when the ML605 boar d is installed into a PC motherboa rd.
ML605 Hardware User Guide www .xilinx.com 47 UG534 (v1.2.1) January 21, 2010 Detailed Des cription FPGA INIT and DONE LEDs The typical Xilinx FPGA power up and conf iguration status LEDs are pr esent on the ML605. The red INIT LED DS31 comes on momentarily after the FPGA powers up and during its internal power -on process.
48 www .xilinx.com ML6 05 Hard ware User Guid e UG534 (v1.2.1) January 21 , 2010 Chapter 1: ML605 Ev aluation Board User LEDs The ML605 provides two gr oups of active-High LEDs as described in Figure 1- 18 and Ta b l e 1 - 2 1 . Note: See “User Pushbutton Switches, ” page 49 for more details about the LEDs.
ML605 Hardware User Guide www .xilinx.com 49 UG534 (v1.2.1) January 21, 2010 Detailed Des cription User Pushb utton Switches The ML605 provides six active -High pushbutton sw itches: • SW5, SW6, SW7.
50 www .xilinx.com ML6 05 Hard ware User Guid e UG534 (v1.2.1) January 21 , 2010 Chapter 1: ML605 Ev aluation Board User DIP Switch The ML605 includes an active-High eigh t pole DIP swit ch as described in Figure 1-20 and Ta b l e 1 - 2 3 .
ML605 Hardware User Guide www .xilinx.com 51 UG534 (v1.2.1) January 21, 2010 Detailed Des cription User SMA GPIO The ML605 includes an pair of SMA connectors for GPIO as described in Figure 1-21 and Ta b l e 1 - 2 4 .
52 www .xilinx.com ML6 05 Hard ware User Guid e UG534 (v1.2.1) January 21 , 2010 Chapter 1: ML605 Ev aluation Board LCD Displa y (16 C haracter x 2 Lines) The ML605 board has a 16-character x 2-line LCD (Display T e ch S162D BA BC, installed onto J41 2x7 header) on the board to display text information.
ML605 Hardware User Guide www .xilinx.com 53 UG534 (v1.2.1) January 21, 2010 Detailed Des cription 1 8 . Switches The ML605 Evalua tion board includes the foll owing switches: • Power On/Off Slide S.
54 www .xilinx.com ML6 05 Hard ware User Guid e UG534 (v1.2.1) January 21 , 2010 Chapter 1: ML605 Ev aluation Board FPGA_PROG_B Pushbut ton SW4 (Activ e-Low) This switch grounds the FPGA's PR OG_B pin wh en pressed. This action clears the FPGA. See the V irtex-6 FPGA Data Sheet for mor e information on clearing the contents of the FPGA.
ML605 Hardware User Guide www .xilinx.com 55 UG534 (v1.2.1) January 21, 2010 Detailed Des cription System A CE CF CompactFlash Image Select DIP Switch S1 System ACE CF CompactFlash (CF) image select DIP switch S1, switch es 1–3, select which CF resident bitstream image is downloaded to the FPGA ( Figure 1-26 ).
56 www .xilinx.com ML6 05 Hard ware User Guid e UG534 (v1.2.1) January 21 , 2010 Chapter 1: ML605 Ev aluation Board Mode, Osc Enab le, Boot EEPROM Select, and Addr Select D IP Switch S2 DIP switch S2 is a multi-purpose selector switch ( Figure 1-27 and T able 1-27, p age 57 ).
ML605 Hardware User Guide www .xilinx.com 57 UG534 (v1.2.1) January 21, 2010 Detailed Des cription See “3. 128 Mb Platform Flash XL,” page 20 and “4.
58 www .xilinx.com ML6 05 Hard ware User Guid e UG534 (v1.2.1) January 21 , 2010 Chapter 1: ML605 Ev aluation Board Note: The ML605 board V ADJ voltage for the FMC HPC and LPC connectors (J64 and J63) is fixed at 2.5V (non-adjusta ble). The 2.5V rail cannot b e tur ned off.
ML605 Hardware User Guide www .xilinx.com 59 UG534 (v1.2.1) January 21, 2010 Detailed Des cription C14 FMC_HPC_LA10_P AM20 D14 FMC_HPC_LA09_P AM18 C15 FMC_HPC_LA10_N AL20 D15 FMC_HPC_LA09_N AL18 C18 F.
60 www .xilinx.com ML6 05 Hard ware User Guid e UG534 (v1.2.1) January 21 , 2010 Chapter 1: ML605 Ev aluation Board E28 FMC_HPC_HB09_N AK34 F28 FMC_HPC_HB08_P AK33 E30 FMC_HPC_HB13_P AH33 F29 FMC_HPC_.
ML605 Hardware User Guide www .xilinx.com 61 UG534 (v1.2.1) January 21, 2010 Detailed Des cription J2 FMC_HPC_CLK3_M2C_P (2) U84.6 K4 FMC_HPC_CLK2_M2C _P (2) U83.
62 www .xilinx.com ML6 05 Hard ware User Guid e UG534 (v1.2.1) January 21 , 2010 Chapter 1: ML605 Ev aluation Board T able 1-29 : P o wer Supply V oltages for HPC Connector Vo l t a g e S u p p l y Allowable Vo l t a g e R a n g e No Pins Max Amps T olerance Max Capacitive Load V ADJ Fixed 2.
ML605 Hardware User Guide www .xilinx.com 63 UG534 (v1.2.1) January 21, 2010 Detailed Des cription 20. VIT A 57.1 FMC LPC Connector The ML605 implements both the High Pin Coun t (HPC, J64) and Low Pin Count (LPC, J63) connector options of VIT A 57.1.1 FMC specific ation.
64 www .xilinx.com ML6 05 Hard ware User Guid e UG534 (v1.2.1) January 21 , 2010 Chapter 1: ML605 Ev aluation Board Ta b l e 1 - 3 0 shows the VIT A 57.1 FMC LPC connections. The connector pinout is in Appendix B, “VIT A 57 .1 FMC LPC (J6 3 ) and HPC (J64) Connector Pinout.
ML605 Hardware User Guide www .xilinx.com 65 UG534 (v1.2.1) January 21, 2010 Detailed Des cription Ref erences See the data sheet for the ROHS compliant FMC HPC Samtec SEARA Y connector (carrier side socket ASP-134486-01; module side plug ASP-134488-01), and the high-speed characterization report for this conne ctor system on the Samtec website.
66 www .xilinx.com ML6 05 Hard ware User Guid e UG534 (v1.2.1) January 21 , 2010 Chapter 1: ML605 Ev aluation Board Onboard P ow er Regulation Figure 1- 28 shows the ML605 onboar d power supply architectur e. The ML605 uses power solutions fr om T exas Instruments.
ML605 Hardware User Guide www .xilinx.com 67 UG534 (v1.2.1) January 21, 2010 Detailed Des cription V o ltage and current monitoring and contr ol ar e available for selected power rails through T exas Instruments’ Fusion Digital Power™ gr aphical user interface (GUI).
68 www .xilinx.com ML6 05 Hard ware User Guid e UG534 (v1.2.1) January 21 , 2010 Chapter 1: ML605 Ev aluation Board 22. System Monitor The System Monitor provides information r egarding the FPGA on-chip temperature and power supply conditions via JT AG and an inte rnal FPGA interface.
ML605 Hardware User Guide www .xilinx.com 69 UG534 (v1.2.1) January 21, 2010 Detailed Des cription System Monitor Header (J35) Figure 1- 30 shows the pinout for the System Monitor 12-pin he ader . The header pr ovides user access to the analog power supply (A Vdd ) and the 1.
70 www .xilinx.com ML6 05 Hard ware User Guid e UG534 (v1.2.1) January 21 , 2010 Chapter 1: ML605 Ev aluation Board ML605 Board P ower Mo nitor In addition to monitoring the FPGA core supply power consumption, two a uxiliary analog input channels (of the 16 that are available) are used to implement a power monitor for the entire ML605 boar d.
ML605 Hardware User Guide www .xilinx.com 71 UG534 (v1.2.1) January 21, 2010 Detailed Des cription F an Controller In highly demanding situations , active thermal management in the form of a heat sink and fan may be requi red. In or der to support this, drive cir cuitry for an external fan has been provided on the ML605.
72 www .xilinx.com ML6 05 Hard ware User Guid e UG534 (v1.2.1) January 21 , 2010 Chapter 1: ML605 Ev aluation Board FPGA P ower Supply Mar gining The PMBus (IIC), which provides access to th e 2 x UDC9240 power controllers, can also be accessed via FPGA I/O in addition to a dedicated header (J3), see Fi gure 1-33 .
ML605 Hardware User Guide www .xilinx.com 73 UG534 (v1.2.1) January 21, 2010 Configuration Options Configuration Options The FPGA on the ML605 Evaluation Board can be configur ed by the following methods: • “3. 128 Mb Platform Flash XL,” page 20 • “4.
74 www .xilinx.com ML6 05 Hard ware User Guid e UG534 (v1.2.1) January 21 , 2010 Chapter 1: ML605 Ev aluation Board.
ML605 Hardware User Guide www .xilinx.com 75 UG534 (v1.2.1) January 21, 2010 Appendix A Default Switch and Jumper Settings Ta b l e A - 1 : Def ault Switch Settings REFDES Function/T ype Default SW2 B.
76 www .xilinx.com ML6 05 Hard ware User Guid e UG534 (v1.2.1) January 21 , 2010 Appendix A: Default Switc h and J umper Settings Ta b l e A - 2 : Def ault Jumper Setting s J umper REFDES Function Def.
ML605 Hardware User Guide www .xilinx.com 77 UG534 (v1.2.1) January 21, 2010 Appendix B VIT A 57.1 FMC LPC (J63) and HPC (J64) Connector Pinout Figure B-1 shows the pinout of the FMC LPC co nnector .
78 www .xilinx.com ML6 05 Hard ware User Guid e UG534 (v1.2.1) January 21 , 2010 Appendix B: VIT A 57.1 FMC LPC (J63) and HPC (J64) Connector Pinout Figure B-2 shows the pinout of the FMC HPC connector .
ML605 Hardware User Guide www .xilinx.com 79 UG534 (v1.2.1) January 21, 2010 Appendix C ML605 Master UCF The UCF template is provided for design s that target the ML605. Net names pr ovided in the constraints below correlate with net names on the ML605 Rev .
80 www .xilinx.com ML6 05 Hard ware User Guid e UG534 (v1.2.1) January 21 , 2010 Appendix C: ML605 Maste r UCF NET "DDR3_D8" LOC = "M13"; ## 21 on J1 NET "DDR3_D9" LOC = .
ML605 Hardware User Guide www .xilinx.com 81 UG534 (v1.2.1) January 21, 2010 NET "DDR3_DQS0_P" LOC = "D12"; ## 12 on J1 NET "DDR3_DQS1_N" LOC = "J12"; ## 27 on .
82 www .xilinx.com ML6 05 Hard ware User Guid e UG534 (v1.2.1) January 21 , 2010 Appendix C: ML605 Maste r UCF NET "FLASH_A21" LOC = "AF9"; ## 10 on U4, A8 on U27 NET "FLASH_A.
ML605 Hardware User Guide www .xilinx.com 83 UG534 (v1.2.1) January 21, 2010 NET "FMC_HPC_DP6_M2C_N" LOC = "AM6"; ## B17 on J64 NET "FMC_HPC_DP6_M2C_P" LOC = "AM5&qu.
84 www .xilinx.com ML6 05 Hard ware User Guid e UG534 (v1.2.1) January 21 , 2010 Appendix C: ML605 Maste r UCF NET "FMC_HPC_HB03_P" LOC = "AL30"; ## E21 on J64 NET "FMC_HPC_HB.
ML605 Hardware User Guide www .xilinx.com 85 UG534 (v1.2.1) January 21, 2010 NET "FMC_HPC_LA16_N" LOC = "AN23"; ## G19 on J64 NET "FMC_HPC_LA16_P" LOC = "AP22";.
86 www .xilinx.com ML6 05 Hard ware User Guid e UG534 (v1.2.1) January 21 , 2010 Appendix C: ML605 Maste r UCF NET "FMC_LPC_LA07_N" LOC = "H32"; ## H14 on J63 NET "FMC_LPC_LA0.
ML605 Hardware User Guide www .xilinx.com 87 UG534 (v1.2.1) January 21, 2010 NET "FPGA_M0" LOC = "U8"; ## 3 on S2 DIP switch (active-High) NET "FPGA_M1" LOC = "W8&qu.
88 www .xilinx.com ML6 05 Hard ware User Guid e UG534 (v1.2.1) January 21 , 2010 Appendix C: ML605 Maste r UCF NET "PCIE_RX2_N" LOC = "L4"; ## B24 on P1 NET "PCIE_RX2_P" .
ML605 Hardware User Guide www .xilinx.com 89 UG534 (v1.2.1) January 21, 2010 NET "PMBUS_DATA_LS" LOC = "AB10"; ## 2 on Q17 ## NET "SFP_LOS" LOC = "V23"; ## 8 on.
90 www .xilinx.com ML6 05 Hard ware User Guid e UG534 (v1.2.1) January 21 , 2010 Appendix C: ML605 Maste r UCF NET "USB_D6_LS" LOC = "V27"; ## 2 on U31 NET "USB_D7_LS" LO.
ML605 Hardware User Guide www .xilinx.com 91 UG534 (v1.2.1) January 21, 2010 Appendix D Refer ences This section provide s refer e nces to document ation supporting V irt ex-6 FPGAs, tools, and IP . For additional informa tion, see www .xilinx.com/support/d ocumentation/index.
92 www .xilinx.com ML6 05 Hard ware User Guid e UG534 (v1.2.1) January 21 , 2010 Appendix D: Ref erences Additional documentation: 22. Micron T echnology , Inc. , DDR3 SODIMM Specification (M T4JSF6464HY - 1G1) 23. Wi n b o n d , Serial Flash Memory Data Sheet ( W25Q64VSF IG) 24.
Een belangrijk punt na aankoop van elk apparaat Xilinx ML605 (of zelfs voordat je het koopt) is om de handleiding te lezen. Dit moeten wij doen vanwege een paar simpele redenen:
Als u nog geen Xilinx ML605 heb gekocht dan nu is een goed moment om kennis te maken met de basisgegevens van het product. Eerst kijk dan naar de eerste pagina\'s van de handleiding, die je hierboven vindt. Je moet daar de belangrijkste technische gegevens Xilinx ML605 vinden. Op dit manier kan je controleren of het apparaat aan jouw behoeften voldoet. Op de volgende pagina's van de handleiding Xilinx ML605 leer je over alle kenmerken van het product en krijg je informatie over de werking. De informatie die je over Xilinx ML605 krijgt, zal je zeker helpen om een besluit over de aankoop te nemen.
In een situatie waarin je al een beziter van Xilinx ML605 bent, maar toch heb je de instructies niet gelezen, moet je het doen voor de hierboven beschreven redenen. Je zult dan weten of je goed de alle beschikbare functies heb gebruikt, en of je fouten heb gemaakt die het leven van de Xilinx ML605 kunnen verkorten.
Maar de belangrijkste taak van de handleiding is om de gebruiker bij het oplossen van problemen te helpen met Xilinx ML605 . Bijna altijd, zal je daar het vinden Troubleshooting met de meest voorkomende storingen en defecten #MANUAl# samen met de instructies over hun opplosinge. Zelfs als je zelf niet kan om het probleem op te lossen, zal de instructie je de weg wijzen naar verdere andere procedure, bijv. door contact met de klantenservice of het dichtstbijzijnde servicecentrum.
