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R LogiCORE™ IP Initiator/T ar g et v5.1 f or PCI-X™ Getting Star ted Guide UG158 Mar ch 24, 2008.
PCI-X v5.1 165 Getting Star ted Guide www .xilinx.com UG158 March 24, 2008 Xilinx is disclosing th is Document and Intellectual Prope r ty (her einafter “the Design”) to you fo r use in the dev elopment of de signs to operate on, or in terface with Xilinx FPGAs.
www .xilinx.com PCI-X v5.1 165 Getting Started Guide UG158 March 24, 2008 04/04/02 2.2.1 Updated trademarks page in ug000_title.fm . 06/24/02 3.0 Initial Xilinx release of corpora te-wide common template set, used f or User Guides, T utorials, Release Notes, Manuals, an d ot her lengthy , multiple-chapter documents created by both CMP and ITP .
PCI-X v5.1 165 Getting Star ted Guide www .xilinx.com UG158 March 24, 2008 10/10/07 9.5 Updated for IP2 Jade Minor release. Added section r egarding configuration pins to device family chapter .
www .xilinx.com PCI-X v5.1 165 Getting Started Guide UG158 March 24, 2008 Schedule of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Preface: About This Guide Guide Contents .
PCI-X v5.1 165 Getting Star ted Guide www .xilinx.com UG158 March 24, 2008 Verilog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 VHDL . . . . . . . . . . . . . . .
www .xilinx.com PCI-X v5.1 165 Getting Started Guide UG158 March 24, 2008 Chapter 1: Getting Started Chapter 2: Licensing the Co re Chapter 3: Family Specific Considerations Figure 3-1: PCI/PCI-X Output Drive r VCCO Generation . . . . . . . . . . . . .
PCI-X v5.1 165 Getting Star ted Guide www .xilinx.com UG158 March 24, 2008.
PCI-X v5.1 165 Getting Star ted Guide www .xilinx.com 9 UG158 March 24, 2008 R Pr eface About This Guide The Initiator/ T arget v5.1 for PCI-X Getting Started Guide provides inf ormation about the Log.
10 www .xilinx.com PCI-X v5.1 165 Getting Started Guide UG158 March 24, 2008 Preface: About This Guide R Con ventions T ypographical The following typographical conventions are used in this document: .
PCI-X v5.1 165 Getting Star ted Guide www .xilinx.com 11 UG158 March 24, 2008 Con ventions R Online Document The following conventions ar e used in this document: Con vention Meaning or Use Example Blue text Cro ss -ref ere nc e li nk to a location in the current document See “Additional Resources” for details.
12 www .xilinx.com PCI-X v5.1 165 Getting Started Guide UG158 March 24, 2008 Preface: About This Guide R.
PCI-X v5.1 165 Getting Star ted Guide www .xilinx.com 13 UG158 March 24, 2008 R Chapter 1 Getting Started The Initiator/T arget core for PCI-X pr ovides a fully verified, pr e-implemented PCI-X bus interface tar geted for devices based on the V irtex architectur e.
14 www .xilinx.com PCI-X v5.1 165 Getting Started Guide UG158 March 24, 2008 Chapter 1: Getting Star ted R Step-by-step instructions using supported de sign tools are pr ovided in this guide to simulate, synthesize, and implement the User app example design.
PCI-X v5.1 165 Getting Star ted Guide www .xilinx.com 15 UG158 March 24, 2008 R Chapter 2 Licensing the Cor e This chapter provides instructions for installing and obtaining a license for the Initiator/T arget cor e for PCI-X, which you must do befor e using it in your designs.
16 www .xilinx.com PCI-X v5.1 165 Getting Started Guide UG158 March 24, 2008 Chapter 2: Licens ing the Core R Full License The Full license is pr ovided when you purchase the core, and pr ovides full access to all core f unctionality both in simulation and in hardwar e, including: • Gate-level functional simulation support.
PCI-X v5.1 165 Getting Star ted Guide www .xilinx.com 17 UG158 March 24, 2008 R Chapter 3 Family Specific Considerations This chapter pr ovides important design information specific to the cor e interface targeting Vi r t e x d e v i c e s .
18 www .xilinx.com PCI-X v5.1 165 Getting Started Guide UG158 March 24, 2008 Chapter 3: Fa mily Sp ecific Considerati ons R 2VP7-FF672-6C/I 66 MHz PCI-X 3.3V 64-bit pcix_lc_64x pcix_core 2vp7ff672_64x.ucf 2VP7-FF672-6C/I 100 MHz PCI-X 3.3V 64-bit pcix_lc_64xf pcix_fast 2vp7ff672_64xf.
PCI-X v5.1 165 Getting Star ted Guide www .xilinx.com 19 UG158 March 24, 2008 Design Support R 2VP40-FF1 152-6C/I 66 MHz PCI-X 3.3V 64-bit pcix_lc_64x pcix_core 2vp40ff1 152_6 4x.ucf 2VP40-FF1 152-6C/I 100 MHz PCI-X 3.3V 64-bit pcix_lc_64xf pcix_fast 2vp40ff1 152_6 4xf.
20 www .xilinx.com PCI-X v5.1 165 Getting Started Guide UG158 March 24, 2008 Chapter 3: Fa mily Sp ecific Considerati ons R Wrapper Files W rapper files contain an instance of the core in terface and its simulation model, as well as the instances of all I/O elements used by the cor e interface.
PCI-X v5.1 165 Getting Star ted Guide www .xilinx.com 21 UG158 March 24, 2008 Device Initialization R Device Initialization Immediately after FPGA config uration, both th e core interface and the user application are initialized by the startup mechanism present in all V irtex devices.
22 www .xilinx.com PCI-X v5.1 165 Getting Started Guide UG158 March 24, 2008 Chapter 3: Fa mily Sp ecific Considerati ons R bitstr eam is in use. When this occurs, external cir cuitry is responsi ble for re- initializing the FPGA and loading an alternate bitstr eam.
PCI-X v5.1 165 Getting Star ted Guide www .xilinx.com 23 UG158 March 24, 2008 Electrical Compliance R It is important to note that the frequency of th is clock is not guaranteed to be constant.
24 www .xilinx.com PCI-X v5.1 165 Getting Started Guide UG158 March 24, 2008 Chapter 3: Fa mily Sp ecific Considerati ons R Input Dela y Buffers Input delay buf fers ar e used to pr ovide guaranteed hold time on all bus inputs when in PCI bus mode.
PCI-X v5.1 165 Getting Star ted Guide www .xilinx.com 25 UG158 March 24, 2008 Generating Bi tstreams R Generating Bitstreams The bitstream generation pr ogram, bitgen, may issue DRC warnings when generating bitstr eams for PCI-X designs. The number of these warnings varies depending on the configuration options used fo r the PCI-X core.
26 www .xilinx.com PCI-X v5.1 165 Getting Started Guide UG158 March 24, 2008 Chapter 3: Fa mily Sp ecific Considerati ons R.
PCI-X v5.1 165 Getting Star ted Guide www .xilinx.com 27 UG158 March 24, 2008 R Chapter 4 Functional Simulation This chapter describes how to simulate the User app example design using the supported functional simulation tools. If you ar e usin g a design with refer ence clocks, substitute pcix_top with pcix_top_r and test_tb with test_tb_r .
28 www .xilinx.com PCI-X v5.1 165 Getting Started Guide UG158 March 24, 2008 Chapter 4: Functional Sim ulation R ../../src/xpci/pcix_lc.v ../../src/xpci/pcix_core.
PCI-X v5.1 165 Getting Star ted Guide www .xilinx.com 29 UG158 March 24, 2008 Mentor Graphics ModelSim R Most of the files listed ar e related to the exampl e design and its test bench. For other test benches, the following subset must be used for proper simulation of the cor e interface: .
30 www .xilinx.com PCI-X v5.1 165 Getting Started Guide UG158 March 24, 2008 Chapter 4: Functional Sim ulation R vlib simprim vcom -93 -work simprim <Xilinx Install Path>/vhdl/src/simprims/simprim_Vpackage_mti.vhd vcom -93 -work simprim <Xilinx Install Path>/vhdl/src/simprims/simprim_Vcomponents_mti.
PCI-X v5.1 165 Getting Star ted Guide www .xilinx.com 31 UG158 March 24, 2008 R Chapter 5 Synthesizing a Design This chapter describes the use of supported synthesis tools usi ng the Use rapp example design for step-by-step ins tructions and illustrations.
32 www .xilinx.com PCI-X v5.1 165 Getting Started Guide UG158 March 24, 2008 Chapter 5: Synthesizing a Design R 2. Under File T ype, select Proje ct File and enter the proje ct name ( flowtest in this example) and synthesis directory: <Install Path>/verilog/example/synth esis 3.
PCI-X v5.1 165 Getting Star ted Guide www .xilinx.com 33 UG158 March 24, 2008 Synplicity Synplify R 5. Navigate to the virtex.v file ( Figur e 5-3 ); then click Add to move this source file into the Files T o Add list . The next files ar e located in: <Install Path>/verilog/src/xpci 6.
34 www .xilinx.com PCI-X v5.1 165 Getting Started Guide UG158 March 24, 2008 Chapter 5: Synthesizing a Design R 7. Navigate to the source dir ectory ( Figure 5-5 ), select the cfg_test_s.
PCI-X v5.1 165 Getting Star ted Guide www .xilinx.com 35 UG158 March 24, 2008 Synplicity Synplify R 10. Click Change Result File to display the EDIF Result File dialog box; then move the to following dir ectory: <Install Path>/verilog/example/synth esis 11 .
36 www .xilinx.com PCI-X v5.1 165 Getting Started Guide UG158 March 24, 2008 Chapter 5: Synthesizing a Design R 15. On the Implementation Results tab, de select W rite V endor Constraint File. 16. Click OK to return to the main pr oject window . 17. From the main pr oject window , click Run.
PCI-X v5.1 165 Getting Star ted Guide www .xilinx.com 37 UG158 March 24, 2008 Synplicity Synplify R 3. Click OK to exit the dialog and r e turn to the pr oject window ( Figur e 5-10 ).
38 www .xilinx.com PCI-X v5.1 165 Getting Started Guide UG158 March 24, 2008 Chapter 5: Synthesizing a Design R The next files ar e located in: <Install Path>/vhdl/src/xpci 6. Navigate to the xpci directory ( Fi gure 5-12 ) , select the si mulation model and the wrapper files (pcix_cor e.
PCI-X v5.1 165 Getting Star ted Guide www .xilinx.com 39 UG158 March 24, 2008 Synplicity Synplify R 8. In the Sour ce Files list, view the list of newly added sour ce files by double-clicking the flowtest/vhdl folder (if it is not already open). Drag to reorder the sour ce files in the hierarchical or der shown in Figure 5-14 .
40 www .xilinx.com PCI-X v5.1 165 Getting Started Guide UG158 March 24, 2008 Chapter 5: Synthesizing a Design R 1 1. From the main project window , click Change T arget to display the Options for Implementation dialog box, as shown in Figure 5-15 . 12.
PCI-X v5.1 165 Getting Star ted Guide www .xilinx.com 41 UG158 March 24, 2008 Xilinx XST R Note: if you run LeonardoSpectr um with the graphical us er interf ace, the quick setup f or m cannot be used to synthesize the design. Instead, c hoose File > Run Script from the menu.
42 www .xilinx.com PCI-X v5.1 165 Getting Started Guide UG158 March 24, 2008 Chapter 5: Synthesizing a Design R.
PCI-X v5.1 165 Getting Star ted Guide www .xilinx.com 43 UG158 March 24, 2008 R Chapter 6 Implementing a Design This chapter describes the use of support ed FPGA implementati on tools using the Userapp example design. If you are using a desi g n w it h ref ere nc e cl oc ks , su bs ti tut e pcix_top with pcix_top_r and test_tb with test_tb_r .
44 www .xilinx.com PCI-X v5.1 165 Getting Started Guide UG158 March 24, 2008 Chapter 6: Implementing a Design R ♦ The trce command performs a static ti ming analysis based on the d esign constraints originally specified in the us er constraints file.
PCI-X v5.1 165 Getting Star ted Guide www .xilinx.com 45 UG158 March 24, 2008 R Chapter 7 T iming Simulation This chapter describes the use of support ed timing simulation tools using the Userapp example design. If you are using a desi g n w it h ref ere nc e cl oc ks , su bs ti tut e pcix_top with pcix_top_r and test_tb with test_tb_r .
46 www .xilinx.com PCI-X v5.1 165 Getting Started Guide UG158 March 24, 2008 Chapter 7: Timing Simulation R The SimV ision browser may be used to view si mulation r esults.
PCI-X v5.1 165 Getting Star ted Guide www .xilinx.com 47 UG158 March 24, 2008 Mentor Graphics ModelSim R 3. Invoke ModelSim, and ensur e that the current dir ectory is set to: <Install Path>/vhdl/example/post_sim 4. Create the Si mPrim and UniSim libraries .
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