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R PicoBlaz e 8-bit Embed ded Micr ocontr oller User Guide f o r Spar tan-3, Vir te x-II, and Vir tex -II Pr o FPGA s UG129 (v 1.1.2) J une 24, 2008.
Pico Blaz e 8- bit Em bedded Microco ntrolle r www .xilinx.c om UG129 (v1.1.2) J u ne 24, 200 8 Xilinx is disclos ing this D ocument and Intell ectual Prop er ty (he reinafter “ the Desig n”) to you for use in the deve lopment of de signs t o op er ate on, or interface with Xilin x FPGAs.
Pico Blaz e 8- bit Em bedded Microco ntrolle r www .xilinx.c om 3 UG129 (v 1.1.2) J une 24, 200 8 R Pr eface Limitations Limited W arranty and Disclaimer These design s are provided to you “ as-is”.
4 www .xilinx.c om PicoBlaze 8- bit Embedde d Micr oco ntrol ler UG129 (v 1.1.2) J une 24, 200 8 Preface: Acknow ledgmen ts R Acknowledgments Xilinx tha nks the follow ing individual s fo r their cont.
Pico Blaz e 8- bit Em bedded Microco ntrolle r www .xilinx.c om 5 UG129 (v 1.1.2) J une 24, 200 8 Guide Con tents R About This Guide The PicoBlaze™ em bedded micro contro ller is an eff icient, cost-ef fec tive embedded processor cor e for Spartan ® -3, V irtex ® -II, and V irtex-II Pro FPGAs.
6 www .xilinx.c om PicoBlaze 8- bit Embedde d Micr oco ntrol ler UG129 (v 1.1.2) J une 24, 200 8 Preface: About This Guide R.
Pico Blaz e 8- bit Em bedded Microco ntrolle r www .xilinx.c om 7 UG129 (v 1.1.2) J une 24, 200 8 Preface: Limitati ons Limited Warranty and Disclaimer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Limitation of Liabil ity .
8 www .xilinx.c om PicoBlaze 8- bit Embedde d Micr oco ntrol ler UG129 (v 1.1.2) J une 24, 200 8 R Increment/Decrement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Negate . . . . . . . . . . . .
Pico Blaz e 8- bit Em bedded Microco ntrolle r www .xilinx.c om 9 UG129 (v 1.1.2) J une 24, 200 8 R Chapter 8: Performanc e Input Clock Freq uency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10 www .xilinx.c om PicoBlaze 8- bit Embedde d Micr oco ntrol ler UG129 (v 1.1.2) J une 24, 200 8 R Appendix A: R elated Materials and References App endi x B: Example Progr am Te mpla tes KCPSM3 Syntax . . . . . . . . . . . . . . . . . . . . . . . . .
Pico Blaz e 8- bit Em bedded Microco ntrolle r www .xilinx.c om 11 UG129 (v 1.1.2) J une 24, 200 8 R Chapter 1 Intr oduction The PicoBlaze™ micro controller is a compact, capable, and cost- effective fully embedded 8-bit RIS C microcontrolle r core optimized for the Sp artan ® -3, V irtex ® -II, and V ir tex- II Pro FPGA families.
12 www .xilinx.c om PicoBlaze 8- bit Embedde d Micr oco ntrol ler UG129 (v 1.1.2) J une 24, 200 8 Chapter 1: Intr oduction R • Byte-wide Arit hmetic Logi c Unit (ALU) with CARR Y and ZERO indicator .
Pico Blaz e 8- bit Em bedded Microco ntrolle r www .xilinx.c om 13 UG129 (v 1.1.2) J une 24, 200 8 PicoBlaze Microcontr oller Functional Bloc ks R Other memory organ izations are poss ible to accommodate mor e PicoBlaze contro llers within a single FPG A or to en able intera ctive code updates without recompil ing the FPG A design.
14 www .xilinx.c om PicoBlaze 8- bit Embedde d Micr oco ntrol ler UG129 (v 1.1.2) J une 24, 200 8 Chapter 1: Intr oduction R Progr am Counter (PC) The Program Counter (PC) points to the next instructio n to be executed. By de fault, the PC autom atically increments to the next inst ruction location wh en executing an instruction .
Pico Blaz e 8- bit Em bedded Microco ntrolle r www .xilinx.c om 15 UG129 (v 1.1.2) J une 24, 200 8 Why the PicoBla ze Microcontroller ? R The data registers and scratchpad RAM are not affe cted by Reset. See “RESET Even t” in Append ix C for mor e informa tion.
16 www .xilinx.c om PicoBlaze 8- bit Embedde d Micr oco ntrol ler UG129 (v 1.1.2) J une 24, 200 8 Chapter 1: Intr oduction R performance re quirements. A completely parallel implementation is faster but consumes mo re FP G A res o urc e s. A microcontr oller embedded within the FPGA pr ovides the best of both worlds.
Pico Blaz e 8- bit Em bedded Microco ntrolle r www .xilinx.c om 17 UG129 (v 1.1.2) J une 24, 200 8 R Chapter 2 PicoBlaze Interface Signals The top-level interface sig nals to the PicoBlaz e™ microcontroller appear in Figure 2-1 and are des cribed in Ta b l e 2 - 1 .
18 www .xilinx.c om PicoBlaze 8- bit Embedde d Micr oco ntrol ler UG129 (v 1.1.2) J une 24, 200 8 Chapt er 2: PicoBlaz e Interf ace Signal s R PORT_ID[7: 0] Out put Port Address: Th e I/O port address appears o n this port for two CLK cycles during an INPUT or OUTPUT instruction.
Pico Blaz e 8- bit Em bedded Microco ntrolle r www .xilinx.c om 19 UG129 (v 1.1.2) J une 24, 200 8 R Chapter 3 PicoBlaze Instruction Set Ta b l e 3 - 1 sum marizes the en tire PicoBlaze™ processor inst ruction set, which appe ars alphabetica lly . Instructions are listed using the KCPS M3 syntax.
20 www .xilinx.c om PicoBlaze 8- bit Embedde d Micr oco ntrol ler UG129 (v 1.1.2) J une 24, 200 8 Chap te r 3: PicoBlaz e Instruction S et R ENABLE INTERRUP T (EINT) Enable inter rupt input INTERRUPT_ENAB LE Å 1- - Int errupt Even t As ynchronous int errupt inpu t.
Pico Blaz e 8- bit Em bedded Microco ntrolle r www .xilinx.c om 21 UG129 (v 1.1.2) J une 24, 200 8 R RETURNI DISABLE (RETI DISABLE) Return fr om in terr upt servic e r outine .
22 www .xilinx.c om PicoBlaze 8- bit Embedde d Micr oco ntrol ler UG129 (v 1.1.2) J une 24, 200 8 Chap te r 3: PicoBlaz e Instruction S et R Address Spaces As show n in Ta b l e 3 - 2 , th e PicoBlaze m icro controller has five distinct address spaces .
Pico Blaz e 8- bit Em bedded Microco ntrolle r www .xilinx.c om 23 UG129 (v 1.1.2) J une 24, 200 8 Address Space s R T able 3-2: PicoBl aze Address Sp aces and R elated Inst ructions Address Space Siz.
24 www .xilinx.c om PicoBlaze 8- bit Embedde d Micr oco ntrol ler UG129 (v 1.1.2) J une 24, 200 8 Chap te r 3: PicoBlaz e Instruction S et R Pr ocessing Data All data processing inst ructions operate on any of the 16 general-purpose registers.
Pico Blaz e 8- bit Em bedded Microco ntrolle r www .xilinx.c om 25 UG129 (v 1.1.2) J une 24, 200 8 Pr ocessing Data R Complement/In v er t Register The PicoBlaze microcontroller does not have a specific instruction to invert individual bits within register sX .
26 www .xilinx.c om PicoBlaze 8- bit Embedde d Micr oco ntrol ler UG129 (v 1.1.2) J une 24, 200 8 Chap te r 3: PicoBlaz e Instruction S et R operation. ORi ng register sX with a bit mask sets specific bits, as shown in Figure 3-6 . A ‘1’ in the bit mask sets the corresponding bit in register sX .
Pico Blaz e 8- bit Em bedded Microco ntrolle r www .xilinx.c om 27 UG129 (v 1.1.2) J une 24, 200 8 Pr ocessing Data R See als o: • “ADD sX, Operand —Add Operand to Register sX,” page 91 • .
28 www .xilinx.c om PicoBlaze 8- bit Embedde d Micr oco ntrol ler UG129 (v 1.1.2) J une 24, 200 8 Chap te r 3: PicoBlaz e Instruction S et R If incre menting or decrementing a multi-r egister value—i.e., a 16- bit value—perform the operation usi ng multiple instruction s.
Pico Blaz e 8- bit Em bedded Microco ntrolle r www .xilinx.c om 29 UG129 (v 1.1.2) J une 24, 200 8 Pr ocessing Data R If multiplicatio n performance is important to the application, connect one of th e FPGA ’s 18x18 hardwar e multipliers the PicoBlaze I/O ports, as shown in Figur e 3-15 .
30 www .xilinx.c om PicoBlaze 8- bit Embedde d Micr oco ntrol ler UG129 (v 1.1.2) J une 24, 200 8 Chap te r 3: PicoBlaz e Instruction S et R Division The PicoBlaz e microcon troller cor e does not have a dedicated h ardwar e di vider .
Pico Blaz e 8- bit Em bedded Microco ntrolle r www .xilinx.c om 31 UG129 (v 1.1.2) J une 24, 200 8 Pr ocessing Data R No Oper ation (NOP) The PicoBlaze i nstruction set does no t have a specific NOP instruction .
32 www .xilinx.c om PicoBlaze 8- bit Embedde d Micr oco ntrol ler UG129 (v 1.1.2) J une 24, 200 8 Chap te r 3: PicoBlaz e Instruction S et R A similar NOP techniq ue is to simply jump to th e next instruction, which is equiva lent to the default program flow .
Pico Blaz e 8- bit Em bedded Microco ntrolle r www .xilinx.c om 33 UG129 (v 1.1.2) J une 24, 200 8 Pr ocessing Data R Each bit of r egister sX is logically ANDed wit h either the contents of register sY or a lit eral constant, kk . The operation sets the Z ERO flag if the result of all bitwise AND opera tions is zero.
34 www .xilinx.c om PicoBlaze 8- bit Embedde d Micr oco ntrol ler UG129 (v 1.1.2) J une 24, 200 8 Chap te r 3: PicoBlaz e Instruction S et R The example in Figure 3-25 demonstrates how to generate parit y for all eight bits in a reg i st e r . See also “TEST sX, Operand — T est Bit Location in Register sX, Generate Odd Parity ,” page 11 6 .
Pico Blaz e 8- bit Em bedded Microco ntrolle r www .xilinx.c om 35 UG129 (v 1.1.2) J une 24, 200 8 Pr ocessing Data R See als o: • “SL[ 0 | 1 | X | A ] sX — Shif t Left Regi ster sX,” pa ge 10.
36 www .xilinx.c om PicoBlaze 8- bit Embedde d Micr oco ntrol ler UG129 (v 1.1.2) J une 24, 200 8 Chap te r 3: PicoBlaz e Instruction S et R Mo ving Data Data move ment between va rious resources is an essential mi crocontroller function. Figure 3-26 show s th e va riou s Pic oBla ze i n str uct ions to mo ve data .
Pico Blaz e 8- bit Em bedded Microco ntrolle r www .xilinx.c om 37 UG129 (v 1.1.2) J une 24, 200 8 Progr am Flow Contr ol R The JUMP , CALL , an d RETURN instructions are all conditio nally executed, dependin g if a condition is specified and specifi cally whether the CAR R Y or ZERO flags are set or cleared.
38 www .xilinx.c om PicoBlaze 8- bit Embedde d Micr oco ntrol ler UG129 (v 1.1.2) J une 24, 200 8 Chap te r 3: PicoBlaz e Instruction S et R The JUMP instruction does not af fect the ZERO and CAR R Y flags. All jumps ar e absolute; there ar e no relative jumps.
Pico Blaz e 8- bit Em bedded Microco ntrolle r www .xilinx.c om 39 UG129 (v 1.1.2) J une 24, 200 8 Progr am Flow Contr ol R RETURN instructions themselves.
40 www .xilinx.c om PicoBlaze 8- bit Embedde d Micr oco ntrol ler UG129 (v 1.1.2) J une 24, 200 8 Chap te r 3: PicoBlaz e Instruction S et R.
Pico Blaz e 8- bit Em bedded Microco ntrolle r www .xilinx.c om 41 UG129 (v 1.1.2) J une 24, 200 8 R Chapter 4 Interrupts The Pico Blaz e™ p r oces sor pr o vide s a s ing le in ter ru pt in pu t sig na l.
42 www .xilinx.c om PicoBlaze 8- bit Embedde d Micr oco ntrol ler UG129 (v 1.1.2) J une 24, 200 8 Chapter 4: Interrupts R A special RETURNI command ensur es that the end of an interr upt service routine r estor es the status of the flags and contr ols the enable of futur e interrupts.
Pico Blaz e 8- bit Em bedded Microco ntrolle r www .xilinx.c om 43 UG129 (v 1.1.2) J une 24, 200 8 Example Interrupt Flow R 3. The PicoBlaze microcontr oller recognizes the interrupt and pr eempts the ADD s0,s1 instruction. The current PC, which points to the ADD s0 s1 instruction, is pushed onto the CALL/RETURN stack.
44 www .xilinx.c om PicoBlaze 8- bit Embedde d Micr oco ntrol ler UG129 (v 1.1.2) J une 24, 200 8 Chapter 4: Interrupts R Figure 4-3 shows th e same interrupt procedur e but as a timing diagram. W ith the int errupt enabled, the INTERRUPT input is r ecognized a t Step (2), the same clock cycle where the ADDRESS bus changes va lue.
Pico Blaz e 8- bit Em bedded Microco ntrolle r www .xilinx.c om 45 UG129 (v 1.1.2) J une 24, 200 8 R Chapter 5 Scratchpad RAM The PicoBlaz e™ micr ocontr oller contains a 64-byte s cratchpad R AM. T w o ins tructio ns, STORE and FETCH , move data between any data r egister and the scratchpad R AM.
46 www .xilinx.c om PicoBlaze 8- bit Embedde d Micr oco ntrol ler UG129 (v 1.1.2) J une 24, 200 8 Chap te r 5: Scratc hpad RAM R Impl eme nting a Lo ok-U p T ab le The next few exam ples demonstrate both the flexibility of the scratchpad R AM and indirect ad dress ing.
Pico Blaz e 8- bit Em bedded Microco ntrolle r www .xilinx.c om 47 UG129 (v 1.1.2) J une 24, 200 8 Stack Operat ions R Stack Operations Although the Pi coBlaze microcontroller has a CALL/RETUR N stack, it does not have a dedicated data st ack.
48 www .xilinx.c om PicoBlaze 8- bit Embedde d Micr oco ntrol ler UG129 (v 1.1.2) J une 24, 200 8 Chap te r 5: Scratc hpad RAM R.
Pico Blaz e 8- bit Em bedded Microco ntrolle r www .xilinx.c om 49 UG129 (v 1.1.2) J une 24, 200 8 R Chapter 6 Input and Output Ports The PicoB laze™ microcontroller sup ports up to 256 input ports an d 256 output ports that can also be combined to create in put/ou tput ports.
50 www .xilinx.c om PicoBlaze 8- bit Embedde d Micr oco ntrol ler UG129 (v 1.1.2) J une 24, 200 8 Chapter 6: Input and Output P orts R INPUT Operatio ns An INPUT operation transfers the data supplie d on the IN_PORT input port t o any on e of the 16 data registers, defined by register sX , as shown in Figure 6-1 .
Pico Blaz e 8- bit Em bedded Microco ntrolle r www .xilinx.c om 51 UG129 (v 1.1.2) J une 24, 200 8 INPUT Operations R In this example, the PicoBlaze mi crocontr oller is r eading data fro m the port addr ess defined by the contents of r egister s7 . The r ead data is captured in r egister s0 .
52 www .xilinx.c om PicoBlaze 8- bit Embedde d Micr oco ntrol ler UG129 (v 1.1.2) J une 24, 200 8 Chapter 6: Input and Output P orts R Failure to include a register any where in the path from POR T_ID to IN_P OR T is the most common reason for decrea sed system clock rates.
Pico Blaz e 8- bit Em bedded Microco ntrolle r www .xilinx.c om 53 UG129 (v 1.1.2) J une 24, 200 8 OUTPUT Operations R OUTPUT Operations As show n in Figure 6-5 , an OUTPUT operation pr esents the contents of any of the 16 registers to the OUT_POR T output po rt.
54 www .xilinx.c om PicoBlaze 8- bit Embedde d Micr oco ntrol ler UG129 (v 1.1.2) J une 24, 200 8 Chapter 6: Input and Output P orts R Simple Output St ructure f or F e w Output Destinations For eight or less simple output ports, use “o ne-hot” port addr esses and only decode the appropri ate PO R T_ID sign al, as s hown in Fig ure 6-7 .
Pico Blaz e 8- bit Em bedded Microco ntrolle r www .xilinx.c om 55 UG129 (v 1.1.2) J une 24, 200 8 OUTPUT Operations R As show n in Figure 6-8 , use CONSTANT dire ctives in the program make the code readable and help ensur e that the corre ct ports ar e decoded.
56 www .xilinx.c om PicoBlaze 8- bit Embedde d Micr oco ntrol ler UG129 (v 1.1.2) J une 24, 200 8 Chapter 6: Input and Output P orts R Pipel ining f or Maxim um P erf orm ance In most applications, the PicoBlaze micr ocon troller has more than sufficient performance to meet application requir ements.
Pico Blaz e 8- bit Em bedded Microco ntrolle r www .xilinx.c om 57 UG129 (v 1.1.2) J une 24, 200 8 Pipelining for Maximum P erf ormance R The pipelinin g registers on the OUT_PORT and PORT_ID signals , shaded in Figure 6-9 , are optional. Both OU T_POR T and POR T_ID are valid for two clock cycles.
58 www .xilinx.c om PicoBlaze 8- bit Embedde d Micr oco ntrol ler UG129 (v 1.1.2) J une 24, 200 8 Chapter 6: Input and Output P orts R Repar titioning the Design for Maxim u m P erformance Another appr oach to maximizing performance is to re-evaluate the system requir ements.
Pico Blaz e 8- bit Em bedded Microco ntrolle r www .xilinx.c om 59 UG129 (v 1.1.2) J une 24, 200 8 R Chapter 7 Instruction Storage Configurations The PicoBlaze™ micr ocontroller executes code fr om memory resour ces embedded within the FPGA. Fig ur e 7-1 show s that the PicoBlaze microcontroller actually consists of two subfunctions.
60 www .xilinx.c om PicoBlaze 8- bit Embedde d Micr oco ntrol ler UG129 (v 1.1.2) J une 24, 200 8 Chapter 7: Instruction Stor age Configurations R Stand ar d Configur atio n with U AR T or JT A G Pr o.
Pico Blaz e 8- bit Em bedded Microco ntrolle r www .xilinx.c om 61 UG129 (v 1.1.2) J une 24, 200 8 T wo PicoBlaz e Microcontrollers with S eparate 512x1 8 Code Images in a Block RAM R T wo PicoBlaze M.
62 www .xilinx.c om PicoBlaze 8- bit Embedde d Micr oco ntrol ler UG129 (v 1.1.2) J une 24, 200 8 Chapter 7: Instruction Stor age Configurations R T o maintain com patibility wi th block RAM, the dis tributed ROM must have a registered output using CLB flip-flops.
Pico Blaz e 8- bit Em bedded Microco ntrolle r www .xilinx.c om 63 UG129 (v 1.1.2) J une 24, 200 8 R Chapter 8 Performance Input Clock Frequency Ta b l e 8 - 1 shows the maximum available perform ance for the PicoBlaze™ microcontr oller using various FPG A families and speed grad es.
64 www .xilinx.c om PicoBlaze 8- bit Embedde d Micr oco ntrol ler UG129 (v 1.1.2) J une 24, 200 8 Chapt er 8: P erf ormance R.
Pico Blaz e 8- bit Em bedded Microco ntrolle r www .xilinx.c om 65 UG129 (v 1.1.2) J une 24, 200 8 R Chapter 9 PicoBlaze Development T ools There are thr ee primary development environments for cr eatin g PicoBlaze™ pro cessor applicatio n code, as sum marized in Ta b l e 9 - 1 .
66 www .xilinx.c om PicoBlaze 8- bit Embedde d Micr oco ntrol ler UG129 (v 1.1.2) J une 24, 200 8 Chapter 9: PicoBlaz e Development T ools R Open a DOS b ox and navigate to the wo rking directory . T o assemble the PicoBlaz e program, type: kcpsm3 <filename>[.
Pico Blaz e 8- bit Em bedded Microco ntrolle r www .xilinx.c om 67 UG129 (v 1.1.2) J une 24, 200 8 Mediatr onix pBlazIDE R The assembler al so produces a log file plus files that sho w the assign ments for va rious labels and consta nts found in the source code.
68 www .xilinx.c om PicoBlaze 8- bit Embedde d Micr oco ntrol ler UG129 (v 1.1.2) J une 24, 200 8 Chapter 9: PicoBlaz e Development T ools R Impor ting KCPSM3 Code into pBlazIDE The pBlazID E syntax and in structi on mnemo nics ar e dif fer ent than the Xilinx K CPSM3 syntax.
Pico Blaz e 8- bit Em bedded Microco ntrolle r www .xilinx.c om 69 UG129 (v 1.1.2) J une 24, 200 8 Differences Between the K CPSM3 Asse mbler and pBla zIDE R Differences Between the KCPSM3 Assem bler and pBlazIDE Ta b l e 9 - 2 detai ls the diff erences between the KCPSM3 and pBlazID E instruction mnemo nics.
70 www .xilinx.c om PicoBlaze 8- bit Embedde d Micr oco ntrol ler UG129 (v 1.1.2) J une 24, 200 8 Chapter 9: PicoBlaz e Development T ools R.
Pico Blaz e 8- bit Em bedded Microco ntrolle r www .xilinx.c om 71 UG129 (v 1.1.2) J une 24, 200 8 R Chapter 10 Using the PicoBlaze Micr ocontr oller in an FPGA Design The PicoBlaze ™ microcontr oller is primaril y designed for use in a VHDL desi gn flow .
72 www .xilinx.c om PicoBlaze 8- bit Embedde d Micr oco ntrol ler UG129 (v 1.1.2) J une 24, 200 8 Chapter 10: Usi ng the PicoBlaze Mi cr ocontr oller in an FPGA Design R Connecting the P rogr am R OM The PicoBlaze pr ogram ROM is used w ithin a VHDL design flow .
Pico Blaz e 8- bit Em bedded Microco ntrolle r www .xilinx.c om 73 UG129 (v 1.1.2) J une 24, 200 8 Black Bo x Instan tiation of KCPS M3 using KCP SM3.ngc R Black Bo x Instantiation of KCPSM3 us ing KCPSM3.ngc The Xilinx NGC file included with th e r eferen ce design was g enerated by synthesizing the KCPSM3.
74 www .xilinx.c om PicoBlaze 8- bit Embedde d Micr oco ntrol ler UG129 (v 1.1.2) J une 24, 200 8 Chapter 10: Usi ng the PicoBlaze Mi cr ocontr oller in an FPGA Design R.
Pico Blaz e 8- bit Em bedded Microco ntrolle r www .xilinx.c om 75 UG129 (v 1.1.2) J une 24, 200 8 R Chapter 1 1 Assembler Dir ectives Both the KCPSM3 and pBlazIDE assemblers include dir ectives that pro vide advanced control. Locating Co de at a Specific Address In some cases, application code m ust be assigned to a specific instructio n address.
76 www .xilinx.c om PicoBlaze 8- bit Embedde d Micr oco ntrol ler UG129 (v 1.1.2) J une 24, 200 8 Chap te r 11: Assembler Directives R Defining Co nstants Similar to renaming registers, assign names to con stant values.
Pico Blaz e 8- bit Em bedded Microco ntrolle r www .xilinx.c om 77 UG129 (v 1.1.2) J une 24, 200 8 Defining I/O Po r ts (pBlazIDE) R Input P or ts The DSIN directive defines the name and the por t address (or po rt identification number) for a read-only input po rt.
78 www .xilinx.c om PicoBlaze 8- bit Embedde d Micr oco ntrol ler UG129 (v 1.1.2) J une 24, 200 8 Chap te r 11: Assembler Directives R specifies a te xt file that records the result of any outp ut operatio ns to this d uring instruction se t simulation.
Pico Blaz e 8- bit Em bedded Microco ntrolle r www .xilinx.c om 79 UG129 (v 1.1.2) J une 24, 200 8 Custom Instruction Op-Codes R Dur ing in str uct ion set s imula tio n, p BlazI DE dis pla ys th e r ead able o utpu t por t as s hown in Figure 1 1-8 .
80 www .xilinx.c om PicoBlaze 8- bit Embedde d Micr oco ntrol ler UG129 (v 1.1.2) J une 24, 200 8 Chap te r 11: Assembler Directives R.
Pico Blaz e 8- bit Em bedded Microco ntrolle r www .xilinx.c om 81 UG129 (v 1.1.2) J une 24, 200 8 R Chapter 12 Simulating PicoBlaze Code V a rious tools support PicoBlaze code simulation, each with distinct st r engths and weakne sses as des cribed in T able 12-1 .
82 www .xilinx.c om PicoBlaze 8- bit Embedde d Micr oco ntrol ler UG129 (v 1.1.2) J une 24, 200 8 Chapter 12: Simulating PicoBlaze Code R Furthermore, the pBlazIDE ISS o f fers full single-step and breakpoint support whi le viewing the PicoBlaze assembly source code.
Pico Blaz e 8- bit Em bedded Microco ntrolle r www .xilinx.c om 83 UG129 (v 1.1.2) J une 24, 200 8 Instruction Set Sim ulation with pBlazIDE R Sim ulator Control Butt ons Ta b l e 1 2 - 2 shows the vario us pBlazIDE control buttons and describes thei r functions.
84 www .xilinx.c om PicoBlaze 8- bit Embedde d Micr oco ntrol ler UG129 (v 1.1.2) J une 24, 200 8 Chapter 12: Simulating PicoBlaze Code R Using the pBlazIDE Inst ruction Set Simulator with KCPSM3 Pro gr ams The pBlazIDE so ftware primarily supports on ly a VHDL design flo w , which is su f ficient for many appl ications.
Pico Blaz e 8- bit Em bedded Microco ntrolle r www .xilinx.c om 85 UG129 (v 1.1.2) J une 24, 200 8 T urbocharging Sim ulation using FPGAs! R T urboc har ging Sim u latio n usi ng FP GAs! Har dwa r e si mula tor s tr ack r esults with p ico sec ond or na noseco nd res olu tion .
86 www .xilinx.c om PicoBlaze 8- bit Embedde d Micr oco ntrol ler UG129 (v 1.1.2) J une 24, 200 8 Chapter 12: Simulating PicoBlaze Code R.
Pico Blaz e 8- bit Em bedded Microco ntrolle r www .xilinx.c om 87 UG129 (v 1.1.2) J une 24, 200 8 R Appendix A Related Materials and Refer ences This appendix provides links to a dditional inf ormation relevant to a PicoBlaze™ processor design.
88 www .xilinx.c om PicoBlaze 8- bit Embedde d Micr oco ntrol ler UG129 (v 1.1.2) J une 24, 200 8 Chapter : Re lated Materials and References R.
Pico Blaz e 8- bit Em bedded Microco ntrolle r www .xilinx.c om 89 UG129 (v 1.1.2) J une 24, 200 8 R Appendix B Example Pr ogram T emplates The following code templates pr ovide the basic r ecommended structur e for PicoBlaze™ processor application programs.
90 www .xilinx.c om PicoBlaze 8- bit Embedde d Micr oco ntrol ler UG129 (v 1.1.2) J une 24, 200 8 Appendi x : Exampl e Program T emplate s R pBlazIDE Syntax Figure B-2 provides a code template for creating PicoBlaze applica tions using the pBlazI DE ass embler .
Pico Blaz e 8- bit Em bedded Microco ntrolle r www .xilinx.c om 91 UG129 (v 1.1.2) J une 24, 200 8 R Appendix C PicoBlaze Instruction Set and Event Refer e nce This appendix provides a detailed o perationa l description of each PicoBl aze™ processor instruction and th e Interrupt and Reset events, inclu ding pseudocod e for each instruction.
92 www .xilinx.c om PicoBlaze 8- bit Embedde d Micr oco ntrol ler UG129 (v 1.1.2) J une 24, 200 8 Appen dix : Pico Blaze In struction S et and Event Reference R Pseudocode sX Å (sX + Operand) mod 256.
Pico Blaz e 8- bit Em bedded Microco ntrolle r www .xilinx.c om 93 UG129 (v 1.1.2) J une 24, 200 8 AND sX, Operand — Logical Bitwise AND Registe r sX with Operand R Pseudocode if (CARRY = 1) then sX.
94 www .xilinx.c om PicoBlaze 8- bit Embedde d Micr oco ntrol ler UG129 (v 1.1.2) J une 24, 200 8 Appen dix : Pico Blaze In struction S et and Event Reference R Examples AND sX, sY ; Logically AND the.
Pico Blaz e 8- bit Em bedded Microco ntrolle r www .xilinx.c om 95 UG129 (v 1.1.2) J une 24, 200 8 CALL [Condition,] Addr ess — Call Subroutine a t Specified Address, P ossib ly with Conditions R Condition Depending on the specified Con dition, the program calls the subroutine beginni ng at the specified Address.
96 www .xilinx.c om PicoBlaze 8- bit Embedde d Micr oco ntrol ler UG129 (v 1.1.2) J une 24, 200 8 Appen dix : Pico Blaze In struction S et and Event Reference R COMP ARE sX, Operand — Compare Operand with Re gister sX The COMPARE inst ruct ion pe rforms an 8-bit comparis on of t wo operan ds, as s hown in Figure C-4 .
Pico Blaz e 8- bit Em bedded Microco ntrolle r www .xilinx.c om 97 UG129 (v 1.1.2) J une 24, 200 8 DISABLE INTERRUPT — Disable External Interrupt Input R DISABLE INTERRUPT — Disable External Interrupt Input The DISABLE INTERRUPT instruction clears the interrupt enable (IE) flag.
98 www .xilinx.c om PicoBlaze 8- bit Embedde d Micr oco ntrol ler UG129 (v 1.1.2) J une 24, 200 8 Appen dix : Pico Blaze In struction S et and Event Reference R FETCH sX, Operand — Read Scratchpad RAM Location to Reg ister sX The FETCH instruction r eads s cratchpad RAM location specified by Operand in to register sX , as shown in Figure C-5 .
Pico Blaz e 8- bit Em bedded Microco ntrolle r www .xilinx.c om 99 UG129 (v 1.1.2) J une 24, 200 8 INPUT sX, O perand — S et PORT_ID to Opera nd, Read v alue on IN_ PORT into Register sX R INPUT sX,.
100 www .xilinx.com PicoBla ze 8-bit Em bedded M icr ocontr oller UG129 (v 1.1.2) J une 24, 200 8 Appen dix : Pico Blaze In struction S et and Event Reference R INTERR UPT Event, When En abled The interrupt event is not an instructio n but the response of the PicoBlaze microcontroller to an external i nterrupt input.
Pico Blaz e 8- bit Em bedded Microco ntrolle r www .xilinx.c om 101 UG129 (v 1.1.2) J une 24, 200 8 JUMP [Condition,] Address — J ump to Specified Addr ess, P ossibl y with Conditions R JUMP [Condit.
102 www .xilinx.com PicoBla ze 8-bit Em bedded M icr ocontr oller UG129 (v 1.1.2) J une 24, 200 8 Appen dix : Pico Blaze In struction S et and Event Reference R LO AD sX, Operand — L oad Register sX with Op erand The LOAD instruction load s the contents of any register .
Pico Blaz e 8- bit Em bedded Microco ntrolle r www .xilinx.c om 103 UG129 (v 1.1.2) J une 24, 200 8 OR sX, Operand — Logical Bitwise OR Register sX with Operand R OR sX, Operand — Logical Bitwise OR R egister sX with Operand The OR instruction performs a bitwise logical OR operation between two operands, as shown in Figure C-6 .
104 www .xilinx.com PicoBla ze 8-bit Em bedded M icr ocontr oller UG129 (v 1.1.2) J une 24, 200 8 Appen dix : Pico Blaze In struction S et and Event Reference R OUTPUT sX, Op erand — Write Register .
Pico Blaz e 8- bit Em bedded Microco ntrolle r www .xilinx.c om 105 UG129 (v 1.1.2) J une 24, 200 8 RESET Ev ent R RESET Event The reset event is not an instruction but the response of the Pico Blaze microcontroller when the RESET in put is High.
106 www .xilinx.com PicoBla ze 8-bit Em bedded M icr ocontr oller UG129 (v 1.1.2) J une 24, 200 8 Appen dix : Pico Blaze In struction S et and Event Reference R RETURN [Con dition] — Return from Subroutine Call, P os sibl y with Condition s The RETURN instruction is the compl ement to the CALL ins truction.
Pico Blaz e 8- bit Em bedded Microco ntrolle r www .xilinx.c om 107 UG129 (v 1.1.2) J une 24, 200 8 RETURNI [ENABLE/DISABLE] — Return from Interr upt Service Routine and Enable or Dis able R PBlazID.
108 www .xilinx.com PicoBla ze 8-bit Em bedded M icr ocontr oller UG129 (v 1.1.2) J une 24, 200 8 Appen dix : Pico Blaze In struction S et and Event Reference R RL sX — Rot ate Left Register sX The rotate left instruction operates on any sing le data r egister .
Pico Blaz e 8- bit Em bedded Microco ntrolle r www .xilinx.c om 109 UG129 (v 1.1.2) J une 24, 200 8 SL[ 0 | 1 | X | A ] sX — S hift Lef t Reg ist er sX R Example RR sX; Rotate right.
110 www .xilinx.com PicoBla ze 8-bit Em bedded M icr ocontr oller UG129 (v 1.1.2) J une 24, 200 8 Appen dix : Pico Blaze In struction S et and Event Reference R Examples SL0 sX; Shift left. 0 shifts into LSB, MSB shifts into CARRY. SL1 sX; Shift left.
Pico Blaz e 8- bit Em bedded Microco ntrolle r www .xilinx.c om 111 UG129 (v 1.1.2) J une 24, 200 8 SR[ 0 | 1 | X | A ] sX — Shift Ri ght Register sX R The ZERO flag is alwa ys 0 afte r executing th e SR1 instruction beca use re gister sX is never zero.
112 www .xilinx.com PicoBla ze 8-bit Em bedded M icr ocontr oller UG129 (v 1.1.2) J une 24, 200 8 Appen dix : Pico Blaze In struction S et and Event Reference R Registers/Flags Al tered Register s: sX.
Pico Blaz e 8- bit Em bedded Microco ntrolle r www .xilinx.c om 113 UG129 (v 1.1.2) J une 24, 200 8 SUB sX, O perand —Su btract O perand from Regi ster sX R The STORE instruction is only s upported on PicoBlaze mi cr ocontrollers for Spartan -3, V irtex-II, and V irtex-II Pro FPGAs.
114 www .xilinx.com PicoBla ze 8-bit Em bedded M icr ocontr oller UG129 (v 1.1.2) J une 24, 200 8 Appen dix : Pico Blaze In struction S et and Event Reference R Pseudocode sX Å (sX – Operand) mod 2.
Pico Blaz e 8- bit Em bedded Microco ntrolle r www .xilinx.c om 115 UG129 (v 1.1.2) J une 24, 200 8 SUBCY sX, Operand —Subtract Operand from Re gister sX with Borro w R Description Operand an d CARR Y flag ar e subtracted fr om r egi ster sX . The Z ERO an d CA RR Y flag s are set appropriately .
116 www .xilinx.com PicoBla ze 8-bit Em bedded M icr ocontr oller UG129 (v 1.1.2) J une 24, 200 8 Appen dix : Pico Blaze In struction S et and Event Reference R TEST sX, Operand — T est Bit Loc ation in Register sX, Ge nerate Odd P arity The TEST inst ruct ion p erfo rms t wo rel ated but separ ate oper atio ns.
Pico Blaz e 8- bit Em bedded Microco ntrolle r www .xilinx.c om 117 UG129 (v 1.1.2) J une 24, 200 8 TEST sX, Operand — T est Bit Location in Register sX, Generate Odd P arity R Pseudocode ; logicall.
118 www .xilinx.com PicoBla ze 8-bit Em bedded M icr ocontr oller UG129 (v 1.1.2) J une 24, 200 8 Appen dix : Pico Blaze In struction S et and Event Reference R XOR sX, Operand — Logical Bitwise XOR Register sX with Operand The XOR instruction performs a bitwise logical XOR operation between two o perands, as shown in Fig ure C-13 .
Pico Blaz e 8- bit Em bedded Microco ntrolle r www .xilinx.c om 119 UG129 (v 1.1.2) J une 24, 200 8 R Appendix D Instruction Codes Ta b l e D - 1 provides the 18-bit i nstruction code for every P icoBlaze™ processor instruction.
120 www .xilinx.com PicoBla ze 8-bit Em bedded M icr ocontr oller UG129 (v 1.1.2) J une 24, 200 8 Append ix : Instruction Codes R JUMP Z 11010100aa aaaaaaaa LOAD sX,kk 0 0 0 0 0 0 x x x x k k k k k k .
Pico Blaz e 8- bit Em bedded Microco ntrolle r www .xilinx.c om 121 UG129 (v 1.1.2) J une 24, 200 8 R XOR sX,kk 0 0 1 1 1 0 x x x x k k k k k k k k XOR sX,sY 0 0 1 1 1 1 x x x x y y y y 0 0 0 0 Ta b l.
122 www .xilinx.com PicoBla ze 8-bit Em bedded M icr ocontr oller UG129 (v 1.1.2) J une 24, 200 8 Append ix : Instruction Codes R.
Pico Blaz e 8- bit Em bedded Microco ntrolle r www .xilinx.c om 123 UG129 (v 1.1.2) J une 24, 200 8 R Appendix E Register and Scratc hpad RAM Planning W orksheets This appendix provides worksh eets to plan register assign ment and alloca tion for a PicoBlaz e™ pr ocess or applic ation.
124 www .xilinx.com PicoBla ze 8-bit Em bedded M icr ocontr oller UG129 (v 1.1.2) J une 24, 200 8 Appendi x : Register and Scratc hpad RAM Planning W orksheets R Scratchpad RAM Loc.
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