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EM78P156N OTP ROM EM78P156N 8-BIT MICRO-CONTROLLER Version 1.2 WW W .100 Y .COM.TW WW W .100 Y .COM.TW WW W .100 Y .COM.TW WW W .100 Y .COM.TW WW W .100 Y .COM.TW WW W .100 Y .COM.TW WW W .100 Y .COM.TW WW W .100 Y .COM.TW WW W .100 Y .COM.TW WW W .100 Y .
EM78P156N OTP ROM Specification Revision History Version Content 1.0 Initial version 1.1 Change Power on reset content 07/01/2003 1.2 Add the Device Characteri stic at section 6.3 07/29/2004 Application Note AN-001 EM78P156N v.s. EM78P156E on the DC Characteristics This specification is subject to ch ange without prior notice.
EM78P156N OTP ROM 1. GENERAL DESCRIPTION EM78P156N is an 8-bit microprocessor designed a nd developed with low-power, high-spee d CMOS technology.. It is equipped with 1K*13-bits Electri cal One Time Programmable Read Only Memory (OTP-ROM). It provides three PROTEC TION bits to prevent user’s code in the OTP memory from being intruded.
EM78P156N OTP ROM 2. FEATURES • Operating voltage range : 2.5V~5.5V • Operating temperature range: -40 ° C~85 ° C • Operating frequency rang (base on 2 clocks ): * Crystal mode: DC~20MHz at 5V, DC~ 8MHz at 3V, DC~4MHz at 2.5V. * ERC mode: DC~4MHz at 5V, DC~4M Hz at 3V, DC~4MHz at 2.
EM78P156N OTP ROM * 20 pin SSOP 209mil : EM78P156NKM • 99.9% single instruction cycle commands • The transient point of system fr equency between HXT and LXT is around 400KHz This specification is subject to ch ange without prior notice. 5 07.29.2004 (V1.
EM78P156N OTP ROM 3. PIN ASSIGNMENTS TCC VDD Vss P50 P51 P53 P60/IN T P61 P62 P63 P6 4 P52 /RESET OSCI OSCO P67 P66 P65 EM78P156NP EM78P156NM 1 2 3 4 5 6 7 8 9 16 15 14 13 12 11 10 17 18 TCC VDD Vss P.
EM78P156N OTP ROM T able 2 EM78P156NAS Pin Description Symbol Pin No. Type Function VDD 15 - * Power supply. OSCI 17 I * XTAL type: Crystal input terminal or external clock input pin. * ERC type: RC oscillator input pin. OSCO 16 I/O * XTAL type: Output terminal for crystal oscillator or external clock in put pin.
EM78P156N OTP ROM 4. FUNCTION DESCRIPTION Interrupt Controlle r ROM Instruc tion Registe r Instructio n Decoder R2 ALU Stack ACC R3 R4 Oscil lator/Tim ing Control WDT ti mer Pr escaler R1(TCC) RAM DATA & CONTROL BUS OSCI OSCO /RES ET TCC /INT I/O POR T 6 IOC6 R6 P60//INT P61 P62 P63 P64 P65 P66 P67 I/O POR T 5 IOC5 R5 P50 P51 P52 P53 IOCA Fig.
EM78P156N OTP ROM 3. R2 (Program Counter) & Stack • Depending on the device type, R2 and hardware stack are 10-bits wide. The structure is depicted in Fig.3. • Generating 1024 × 13 bits on-chip OTP ROM add resses to the relative programming in struction codes.
EM78P156N OTP ROM Address R P AGE registers IOC P AGE registers 00 R0 (IAR) Reserve 01 R1 (TCC) CONT (Control Register) 02 R2 (PC) Reserve 03 R3 (S tatus) Reserv e 04 R4 (RSR) Reserve 05 R5 (Port5) IO.
EM78P156N OTP ROM 4. R3 (Status Register) 7 6 5 4 3 2 1 0 GP2 GP1 GP0 T P Z DC C • Bit 0 (C) Carry flag • Bit 1 (DC) Auxiliary carry flag • Bit 2 (Z) Zero flag. Set to "1" if the result of an arithmetic or logic operation is zero. • Bit 3 (P) Power down bit.
EM78P156N OTP ROM • RF can be cleared by instruction but cannot be set. • IOCF is the interrupt mask register. • Note that the result of reading RF is the "logic AND" of RF and IOCF. 8. R10 ~ R3F • All of these are 8-bit general-purpose registers.
EM78P156N OTP ROM • CONT register is both readable and writable. 3. IOC5 ~ IOC6 (I/O Port Control Register) • "1" put the relative I/O pin into high impedance, while "0" defines the relative I/O pin as output. • Only the lower 4 bits of IOC5 can be defined.
EM78P156N OTP ROM • Bit 5 (OD5) Control bit is used to enable the open-drain of P65 pin. • Bit 6 (OD6) Control bit is used to enable the open-drain of P66 pin. • Bit 7 (OD7) Control bit is used to enable the open-drain of P67 pin. • IOCC Register is both readable and writable.
EM78P156N OTP ROM Setting the ROC to "1" will enable the status of R-option pins (P50 ∼ P51) that are read by the controller. Clearing the ROC will di sable the R-option functi on. If the R-option function is selected, user must connect the P51 pin or/and P50 pin to VSS with a 430K Ω external resistor (Rex).
EM78P156N OTP ROM CLK=Fosc/4 is used if CLK bit is "1". If TCC signal source comes from exter nal clock input, TCC is increased by 1 at every falling edge or rising edge of TCC pin. • The watchdog timer is a free runni ng on-chip RC oscillato r .
EM78P156N OTP ROM R-option function is used, it is recommended that P50~ P51 are used as output pi ns. When R-option is in enable state, P50~P51 must be progra mmed as inpu t pins. Under R-option mode, the current/power consumption by Rex should be taken into the consideration to promote energy conservation.
EM78P156N OTP ROM PCRD PCWR PDWR PDRD TIN IOD P61~P67 PORT 0 1 M U X CLK CLK CLK P P P L L L R R R C C C D D D Q Q Q Q Q Q _ _ _ NOTE: Pull-high (down) and Open-drain are not shown in the figure. Fig. 7(b) The Circuit of I/O Port and I/O Control Register for P61~P67 /SLEP T17 T10 T11 IOCE.
EM78P156N OTP ROM Table 4 Usage of Port 6 Input Change Wake-up/Interrupt Function Usage of Port 6 input status changed Wake-up/Interrupt (I) Wake-up from Port 6 Input Status Change (II) Port 6 Input Status Change Interrupt (a) Before SLEEP 1. Read I/O Port 6 (MOV R6,R6) 1.
EM78P156N OTP ROM 4.5 RESET and Wake-up 1. RESET A RESET is initiated by one of the following events- (1) Power on reset. (2) /RESET pin input "low", or (3) WDT time-out (if enabled). The device is kept in a RESET condi tion for a period of approx.
EM78P156N OTP ROM vector following wake-up. If ENI is executed before SL EP, the instruction will begin to execute from the address 008H after wake-up. If DISI is exec uted before SLEP, the operation will rest art from the succee ding instruction right next to SLEP after wake-up.
EM78P156N OTP ROM Table 5 The Summary of the Initialized Values for Registers Address Name Reset Type Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit Name X X X X C53 C52 C51 C50 Power-On U U U U .
EM78P156N OTP ROM Address Name Reset Type Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 /RESET and WDT P P P P P P P P Wake-Up from Pin Change P P P P P P P P Bit Name X X X X X EXIF ICIF TCIF Power.
EM78P156N OTP ROM 1. A power-on condition, 2. A high-low-high pulse on /RESET pin, and 3. Watchdog timer time-out. The values of T and P, listed in Ta ble 4 are used to check how the pro cessor wa kes up. Table 5 shows the events that may affect the status of T and P.
EM78P156N OTP ROM 4.6 Interrupt The EM78P156N has three falling-edge interrupts listed below: (1) TCC overflow interrupt (2) Port 6 Input Status Change Interrupt (3) External interrupt [(P60, /INT) pin]. Before the Port 6 Input Status Change Interrupt is enabled, reading Port 6 (e.
EM78P156N OTP ROM INT ENI/DISI IOD RFWR IOCFRD IOCFWR IRQn IRQm RFRD IOCF /RESET /IRQn VCC RF CLK CLK Q Q D P R L C _ P R L C Q Q _ D Fig. 10 Interrupt Input Circuit 4.
EM78P156N OTP ROM Table 9 The Summary of Maximum Operating Speeds Conditions VDD Fxt max.(MHz) 3.0 8.0 Two cycles with two clocks 5.0 20.0 2. Crystal Oscillator/Cera mic Resonators (XTAL) EM78P156N can be driven by an external clock signal through the OSCI pin as shown in Fig.
EM78P156N OTP ROM T able 10 Capacitor Selection Guide for Cry stal Oscillator or Ceramic Resonator Oscillator Type Frequency Mode Frequency C1(pF) C2(pF) 455 kHz 100~150 100~150 2.0 MHz 20~40 20~40 Ceramic Resonators HXT 4.0 MHz 10~30 10~30 32.768kHz 25 15 100KHz 25 25 LXT 200KHz 25 25 455KHz 20~40 20~150 1.
EM78P156N OTP ROM OSCI EM78P156N Vcc Rext Cext Fig. 13 Circuit for External RC Oscillator Mode Table 11 RC Oscillator Frequencies Cext Rext Average Fosc 5V,25 ° C Average Fosc 3V,25 ° C 3.3k 3.92 MHz 3.65 MHz 5.1k 2.67 MHz 2.60 MHz 10k 1.39MHz 1.40 MHz 20 pF 100k 149 KHz 156 KHz 3.
EM78P156N OTP ROM Word 0 Word 1 Bit12~Bit0 Bit12~Bit0 1. Code Option Register (Word 0) WORD 0 Bit12 Bit11 Bit10 Bit9 Bit8 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 - - - - CLKS ENWDT B - HLF OSC HLP PR2 PR1 PR0 • Bit 12 、 11 、 10 、 9 :Not used. Reserved.
EM78P156N OTP ROM 0 1 1 Enable 1 0 0 Enable 1 0 1 Enable 1 1 0 Enable 1 1 1 Disable 2. Customer ID Register (Word 1) Bit 12~Bit 0 XXXXXXXXXXXXX • Bit 12~0: Customer’s ID code 4.9 Power On Considerations Any microcontroller is not guaranteed to start to oper ate properly b efore the power sup ply stays at its steady state.
EM78P156N OTP ROM EM78P156N / RESET Vdd D R Rin C Fig. 14 External Pow er-Up Reset Circuit 4.11 Residue-Voltage Protection When battery is replaced, device power (Vdd) is take n off but residue -voltage remains. The residue-voltage may trips below Vdd minimum, but not to zero.
EM78P156N OTP ROM EM78P156N / RESET Vdd Q1 Vdd 40K R2 R1 Fig. 16 Circuit 2 for the Residue V oltage Protection 4.12 Instruction Set Each instruction in the inst ruction set is a 13-bit wo rd divided into an OP code and one or m ore operands.
EM78P156N OTP ROM (2) The I/O register can be regard ed a s general regi ster. That is, the same instruction can operate on I/O register. The symbol "R" represents a register designator that specifies whi ch one of the registers (including operational registers and general pu rpose registers) is to be utilized by the instruction.
EM78P156N OTP ROM R(7) → C, C → A(0) 0 0110 11rr rrrr 06rr RLC R R(n) → R(n+1), R(7) → C, C → R(0) C 0 0111 00rr rrrr 07rr SWAPA R R(0-3) → A(4-7), R(4-7) → A(0-3) None 0 0111 01rr rrrr .
EM78P156N OTP ROM 4.13 Timing Diagrams RESET Timing (CLK=" 0") CLK /RESET NOP Instruction 1 Executed Tdr h TCC Input Timing (CLKS= "0") CLK TCC Ttc c Tin s AC Testing : Input is driv en at 2.4V for logic "1",and 0.4V for logic "0".
EM78P156N OTP ROM 5. ABSOLUTE MAXIMUNM RATINGS EM78P156N Items Rating Temperature under bias -40 ° C to 85 ° C Storage temperature -65 ° C to 150 ° C Working voltage 2.5 to 5.5V Working frequency DC to 20MHz* Input voltage Vss-0.3V to Vdd+0.5V Output voltage Vss-0.
EM78P156N OTP ROM 6. ELECTRICAL CHARACTERISTICS 6.1 DC Electrical Characteristic (Ta=25 ° C, VDD=5V ± 5%, VSS=0V) Symbol Parameter Condition Min Typ . Max Unit Two cycle w ith two clocks DC 8.0 MHz FXT XTAL: VDD to 5V T wo cy cle with two clocks DC 20.
EM78P156N OTP ROM 6.2 AC Electrical Characteristic (Ta=25 ° C, VDD=5V ± 5%, VSS=0V) Symbol Parameter Conditions Min Typ Max Unit Dclk Input CLK duty cycle 45 50 55 % Crystal type 100 DC ns Tins Instruction cycle time (CLKS="0") RC type 500 DC ns Ttcc TCC input period (Tins+20)/N* ns Tdrh Device reset hold time 11.
EM78P156N OTP ROM 6.3 Device Characteristic The graphs provided in th e following pages were derived based on a limited number of samples an d are shown here for reference only. The dev ice characterist ic illu strated herein are no t guaranteed for it accuracy.
EM78P156N OTP ROM Vth (Input thershol d voltage) of I/O pins 0 0.5 1 1.5 2 2.5 3 3. 5 4 4.5 5 5.5 VDD (Volt) Vth (Volt) Max(-40 ℃ to 85 ℃ ) Typ 25 ℃ Min(-40 ℃ to 85 ℃ ) Fig. 18 Vth (Threshold voltage) of Port5 v s. VDD This specification is subject to ch ange without prior notice.
EM78P156N OTP ROM Voh/Ioh (5V) -25 -20 -15 -10 -5 0 1 . 522 . 533 . 544 . 55 Voh (V olt) Ioh (mA) Voh/Ioh (3V) -10 -8 -6 -4 -2 0 00 . 511 . 522 . 5 3 Voh (Volt) Ioh (mA) Min 85 ℃ Min 85 ℃ Typ 25 ℃ Typ 25 ℃ Min -40 ℃ Min -40 ℃ Fig. 19 Port5 and Port6 Voh vs.
EM78P156N OTP ROM Vo l / Io l (3 V) 0 5 10 15 20 25 30 35 40 45 00 . 511 . 522 . 53 V o l (V olt) Iol (mA) Vol/Iol (5V) 0 10 20 30 40 50 60 70 80 90 100 0 0.5 1 1.5 2 2.5 3 Vol (Volt) Iol (mA) Typ 25 ℃ Max -40 ℃ Max -40 ℃ Typ 25 ℃ Min 85 ℃ Min 85 ℃ Fig.
EM78P156N OTP ROM WD T Tim e o ut 0 5 10 15 20 25 30 35 40 45 23 456 VDD (Volt ) WDT period (mS) Max 85 ℃ Max 70 ℃ Typ 25 ℃ Min 0 ℃ Min -40 ℃ Fig. 23 WDT time out period vs. VDD, perscaler set to 1:1 WW W .100 Y .COM.TW WW W .100 Y .COM.TW WW W .
EM78P156N OTP ROM Cext = 100pF, Typical RC Frequency vs. VDD 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 3 3.5 4 4.5 5 5.5 VDD (Volt) Frequency (M Hz) R = 3.3K R = 5.1K R = 10K R = 100K Fig. 24 Typical RC OSC Frequency vs. VDD (Cext= 100pF, Temperature at 25 ℃ ) VDD = 5V VDD = 3V Fig.
EM78P156N OTP ROM Four conditions exist with the Operating Current ICC1 to ICC4. These conditions are as follows: ICC1: VDD=3V, Fosc=32K Hz, 2 clocks, WDT disable ICC2: VDD=3V, Fosc=32K Hz, 2 clocks, WDT enable ICC3: VDD=5V, Fosc=4M Hz, 2 clocks, WDT enable ICC4: VDD=5V, Fosc=10M Hz, 2 clocks, WDT enable Typical ICC1 and ICC2 vs.
EM78P156N OTP ROM T ypic al I C C 3 and I C C 4 v s . T e m pe rature 0 0.5 1 1.5 2 2.5 3 3.5 4 -40 -20 0 20 40 60 80 T em p er atu r e ( ℃) Current (mA) T yp ICC4 T yp ICC3 Fig. 28 Typical operating current (ICC3 and ICC4) v s. Temperature Maximum ICC3 and ICC4 vs.
EM78P156N OTP ROM Two conditions exist with the Standby Current I SB1 and ISB2. These condi tions are as follows: ISB1: VDD=5V, WDT disable ISB2: VDD=5V, WDT enable Typical ISB1 and ISB2 vs. Temperature 0 2 4 6 8 10 12 - 4 0 - 2 0 0 2 04 06 08 0 Temperature ( ℃ ) Current (uA) T yp ISB2 T yp ISB1 Fig.
EM78P156N OTP ROM Fig. 32 Operating voltage in temperature range from 0 ℃ to 70 ℃ Fig. 33 Operating voltage in temperature range from -40 ℃ to 85 ℃ This specification is subject to ch ange without prior notice. 49 07.29.2004 (V1.2) WW W .100 Y .
EM78P156N OTP ROM EM78P156N-J HXT V-I 0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 2.25 2.5 2.3 2.8 3.3 3.8 4. 3 4.8 5. 3 Voltage(V) I(mA) Fig. 34 Operating current range (based on high Freq. @ =25 ℃ ) vs. Voltage EM78P156N-J LXT V-I 0 5 10 15 20 25 30 35 2.3 2.
EM78P156N OTP ROM EM78P156N-G HXT V-I 0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 2.25 2.5 2.3 2.8 3.3 3. 8 4.3 4.8 5.3 Voltage(V) I(mA) Fig. 36 Operating current range (based on high Freq. @ =25 ℃ ) vs. Voltage EM78P156N-G LXT V-I 0 5 10 15 20 25 30 35 40 2.
EM78P156N OTP ROM APPENDIX Package Types: OTP MCU Package Type Pin Count Package Size EM78P156NP DIP 18 300 mil EM78P156NM SOP 18 300 mil EM78156NAS SSOP 20 209 mil EM78156NKM SSOP 20 209 mil This specification is subject to ch ange without prior notice.
EM78P156N OTP ROM Package Information 18-Lead Plastic Dual in line (PDIP) — 300 mil This specification is subject to ch ange without prior notice. 53 07.29.2004 (V1.2) WW W .100 Y .COM.TW WW W .100 Y .COM.TW WW W .100 Y .COM.TW WW W .100 Y .COM.TW WW W .
EM78P156N OTP ROM 18-Lead Plastic Small Outline (SOP) — 300 mil This specification is subject to ch ange without prior notice. 54 07.29.2004 (V1.2) WW W .100 Y .COM.TW WW W .100 Y .COM.TW WW W .100 Y .COM.TW WW W .100 Y .COM.TW WW W .100 Y .COM.TW WW W .
EM78P156N OTP ROM 20-Lead Plastic Small Outline (SSOP) — 209 mil This specification is subject to ch ange without prior notice. 55 07.29.2004 (V1.2) WW W .100 Y .COM.TW WW W .100 Y .COM.TW WW W .100 Y .COM.TW WW W .100 Y .COM.TW WW W .100 Y .COM.TW WW W .
EM78P156N OTP ROM Quality Assurance And Reliability Test category Test conditions Remarks Solderability Solder temperature=245 ± 5 ℃， for 5 seconds u p to the sto pp er using a rosin-type flux St.
EM78P156N OTP ROM /Rese Internal POR Power on T p or Tvd Tvr Vdd Symbol Parameter Condition Min. Typ. Max. Unit Tpor Power on reset time Vdd = 5V, -40 ℃ to 85 ℃ 10.
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