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TMS320C3x User ’ s Guide Literature Number: SPRU031E 2558539-9761 revision L July 1997 Printed on Recycled Paper.
IMPORT ANT NOTICE T exas Instruments (TI) reserves the right to make changes to its products or to discontinue any semiconductor product or service without notice, and advises its customers to obtain the latest version of relevant information to verify , before placing orders, that the information being relied on is current.
iii Preface Read This First About This Manual This user ’s guide serves as an applications reference book for the TMS320C3x generation of digital signal processors (DSPs). These include the TMS320C30, TMS320C31, TMS320LC31, and TMS320C32. Throughout the book, all refer- ences to ’C3x refer collectively to the ’C30, ’C31, ’LC31 and ’C32.
Notational Conventions iv In syntax descriptions, the instruction, command, or directive is in bold typeface and parameters are in an italic typeface . Portions of a syntax that are in bold must be entered as shown; portions of a syntax that are in italics describe the type of information that must be entered.
Information About Cautions / Related Documentation from T exas Instruments v Read This First Information About Cautions This book contains cautions. This is an example of a caution statement. A caution statement describes a situation that could potentially damage your software or equipment.
Related Documentation from T exas Instruments / References vi TMS320C3x C Source Debugger User ’s Guide (literature number SPRU053) tells you how to invoke the ’C3x emulator , evaluation module, and simulator versions of the C source debugger interface.
References vii Read This First Digital Signal Processing Applications with the TMS320 Family , V ol. III. T exas Instruments, 1990; Prentice-Hall, Inc., 1990. Gold, Bernard, and Rader , C.M. , Digital Processing of Signals. New Y ork, NY : McGraw-Hill Company , Inc.
References viii Parsons, Thomas., V oice and Speech Processing. New Y ork, NY : McGraw Hill Company , Inc., 1987. Rabiner , Lawrence R., and Schafer , R.W ., Digital Processing of Speech Signals. Englewood Cliffs, NJ: Prentice-Hall, Inc., 1978. Shaughnessy , Douglas.
References ix Read This First Array Signal Processing Haykin, S., Justice, J.H., Owsley , N.L., Y en, J.L., and Kak, A.C. Array Signal Processing. Englewood Cliffs, NJ: Prentice-Hall, Inc., 1985. Hudson, J.E. Adaptive Array Principles. New Y ork, NY : John Wiley and Sons, 1981.
If Y ou Need Assistance x If Y ou Need Assistance . . . World-W ide Web Sites TI Online http://www .ti.com Semiconductor Product Information Center (PIC) http://www .ti.com/sc/docs/pic/home.htm DSP Solutions http://www .ti.com/dsps 320 Hotline On-line http://www .
If Y ou Need Assistance / T rademarks xi Read This First Documentation When making suggestions or reporting errors in documentation, please include the following information that is on the title page: the full title of the book, the publication date, and the literature number .
Contents xiii Contents 1 Introduction 1-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A general description of the TMS320C30, TMS320C31, and TMS320C32, their key features, and typical applications.
Contents xiv 3 CPU Registers 3-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Description of the registers in the CPU register file. 3.1 CPU Multiport Register File 3-2 .
Contents xv Contents 5.3.3 Single-Precision Floating-Point Format 5-7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3.4 Extended-Precision Floating-Point Format 5-8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3.
Contents xvi 7.1.4 RPTS Instruction 7-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.1.5 Repeat-Mode Restrictions 7-6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Contents xvii Contents 9 TMS320C30 and TMS320C31 External-Memory Interface 9-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . Description of primary and expansion interfaces for the ’C30 and ’C31; external interface timing diagrams; programmable wait-states and bank switching.
Contents xviii 1 1.1.3 TMS320C31 Boot-Loading Sequence 1 1-4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.1.4 TMS320C31 Boot Data Stream Structure 1 1-7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.1.5 Interrupt and T rap-V ector Mapping 1 1-1 1 .
Contents xix Contents 12.3.5 TMS320C32 DMA Internal Priority Schemes 12-62 . . . . . . . . . . . . . . . . . . . . . . . . . 12.3.6 CPU and DMA Controller Arbitration 12-63 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.3.7 DMA and Interrupts 12-64 .
Figures xx Figures 1–1 TMS320C3x Devices Block Diagram 1-3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1 TMS320C30 Block Diagram 2-3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figures xxi Contents 5–1 Short-Integer Format and Sign-Extension of Short Integers 5-2 . . . . . . . . . . . . . . . . . . . . . . . . . 5–2 Single-Precision Integer Format 5-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figures xxii 7–8 DMA Interrupt Processing 7-39 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–9 Parallel CPU and DMA Interrupt Processing 7-40 . . . . . . . . . . . . . . . . . . . . . .
Figures xxiii Contents 10–5 STRB1 Control Register 10-8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–6 IOSTRB Control Register 10-9 . . . . . . . . . . . . . . . . . . . . . . . . .
Figures xxiv 1 1–5 Boot-Loader Serial-Port Load Flowchart 1 1-18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1–6 Boot-Loader Memory-Load Flowchart 1 1-19 . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figures xxv Contents 12–41 TMS320C30 and TMS320C31 CPU/DMA Interrupt-Enable Register 12-60 . . . . . . . . . . . . . . . 12–42 TMS320C32 CPU/DMA Interrupt-Enable Register 12-60 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12–43 Mechanism for No DMA Synchronization 12-65 .
T ables xxvi T ables 1–1 TMS320C30, TMS320C31, TMS320LC31, and TMS320C32 Comparison 1-5 . . . . . . . . . . . . 1–2 T ypical Applications of the TMS320 Family 1-7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1 Primary CPU Registers 2-9 .
T ables xxvii Contents 10–2 Data-Access Sequence for a Memory Configuration with T wo Banks 10-14 . . . . . . . . . . . . . . . 10–3 W ait-State Generation 10-16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Examples xxviii Examples 4–1 Pipeline Effects of Modifying the Cache Control Bits 4-23 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–1 Positive Number 5-10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Examples xxix Contents 6–19 Indirect Addressing With Postindex Add and Bit-Reversed Modify 6-17 . . . . . . . . . . . . . . . . . . 6–20 Short-Immediate Addressing 6-18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Examples xxx 12–3 Serial-Port Register Setup #1 12-42 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12–4 Serial-Port Register Setup #1 12-43 . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1-1 Introduction The TMS320C3x generation of digital signal processors (DSPs) are high- performance CMOS 32-bit floating-point devices in the TMS320 family of single-chip DSPs. The ’C3x generation integrates both system control and math-intensive functions on a single controller .
TMS320C3x Devices 1-2 1.1 TMS320C3x Devices The ’C3x family consists of three members: the ’C30, ’C31, and ’C32. The ’C30, ’C31, and ’C32 can perform parallel multiply and arithmetic logic unit (ALU) operations on integer or floating-point data in a single cycle.
TMS320C3x Devices 1-3 Introduction Figure 1–1. TMS320C3x Devices Block Diagram Primary port memory interface Data access 32-bit (’C30-’C31) 8/16/32-bit (’C32) Program access 32-bit (’C30-’.
TMS320C3x Devices 1-4 1.1.4 TMS320C32 The ’C32 is the newest member of the ’C3x generation. They are enhanced versions of the ’C3x family and the lowest cost floating-point processors on the market today .
TMS320C3x Devices 1-5 Introduction T able 1–1. TMS320C30, TMS320C31, TMS320LC31, and TMS320C32 Comparison Memory (words) Cycle On-Chip Off-Chip Peripherals Device Name Freq (MHz) Cycle Time (ns) RAM.
TMS320C3x Devices 1-6 T able 1–1. TMS320C30, TMS320C31, TMS320LC31, and TMS320C32 Comparison (Continued) Memory (words) Cycle On-Chip Off-Chip Peripherals Device Name Freq (MHz) Cycle Time (ns) RAM .
T ypical Applications 1-7 Introduction 1.2 T ypical Applications The TMS320 family’s versatility , realtime performance, and multiple functions offer flexible design approaches in a variety of applications, which are shown in T able 1–2. T able 1–2.
2-1 Architectural Overview This chapter provides an architectural overview of the ’C3x processor . It includes a discussion of the CPU, memory interface, boot loader , peripherals, and direct memory access (DMA) of the ’C3x processor . T opic Page 2.
Overview 2-2 2.1 Overview The ’C3x architecture responds to system demands that are based on sophisti - cated arithmetic algorithms that emphasize both hardware and software solu- tions.
Overview 2-3 Architectural Overview Figure 2–1. TMS320C30 Block Diagram SHZ ARAU0 ARAU1 DISP0, IR0, IR1 ALU 32-bit barrel shifter PC RAM block 1 (1K × 32) ROM block (4K × 32) Cache (64 × 32) RAM .
Overview 2-4 Figure 2–2. TMS320C31 Block Diagram 32-bit barrel shifter ALU 40 24 Boot loader Cache (64 × 32) RAM block 0 (1K × 32) RAM block 1 (1K × 32) RDY HOLD HOLDA STRB R/W D31– D0 A23 – .
Overview 2-5 Architectural Overview Figure 2–3. TMS320C32 Block Diagram 24 24 40 Destination-address register Global-control register Timer0 Timer-period register Timer-counter register Timer-counte.
Central Processing Unit (CPU) 2-6 2.2 Central Processing Unit (CPU) The ’C3x devices (’C30, ’C31, and ’C32) have a register-based CPU architec- ture.
Central Processing Unit (CPU) 2-7 Architectural Overview Figure 2–4. Central Processing Unit (CPU) Multiplexer Multiplier 32-bit barrel shifter Extended- precision registers (R0–R7) Disp † , IR0.
Central Processing Unit (CPU) 2-8 2.2.1 Floating-Point/Integer Multiplier The multiplier performs single-cycle multiplications on 24-bit integer and 32-bit floating-point values. The ’C3x implementation of floating-point arithmetic allows for floating-point or fixed-point operations at speeds up to 33-ns per instruction cycle.
CPU Primary Register File 2-9 Architectural Overview 2.3 CPU Primary Register File The ’C3x provides 28 registers in a multiport register file that is tightly coupled to the CPU.
CPU Primary Register File 2-10 T able 2–1. Primary CPU Registers (Continued) Page Section Assigned Function Register Name IR1 Index register 1 3.1.4 3-4 BK Block-size register 3.1.5 3-4 SP System-stack pointer 3.1.6 3-4 ST Status register 3.1.7 3-5 IE CPU/DMA interrupt-enable regis- ter 3.
CPU Primary Register File 2-1 1 Architectural Overview The ARAU uses the 32-bit block size register (BK) in circular addressing to specify the data block size. The system-stack pointer (SP) is a 32-bit register that contains the address of the top of the system stack.
Other Registers 2-12 2.4 Other Registers The program-counter (PC) is a 32-bit register containing the address of the next instruction to fetch. Although the PC is not part of the CPU register file, it is a register that can be modified by instructions that modify the program flow .
Memory Organization 2-13 Architectural Overview 2.5 Memory Organization The total memory space of the ’C3x is 16M (million) 32-bit words. Program, data, and I/O space are contained within this 16M-word address space, allowing the storage of tables, coefficients, program code, or data in either RAM or ROM.
Memory Organization 2-14 Figure 2–5. Memory Organization of the TMS320C30 RDY HOLD HOLDA STRB R/W D31–D0 A23–A0 XRDY MSTRB IOSTRB XR/W XD31–XD0 XA12–XA0 DMAADDR bus DMADA T A bus DADDR2 bus .
Memory Organization 2-15 Architectural Overview Figure 2–6. Memory Organization of the TMS320C31 RDY HOLD HOLDA STRB R/W D31–D0 A23–A0 DMAADDR bus DMADA T A bus DADDR2 bus DADDR1 bus DDA T A bus.
STRB0_B3/A-1 HOLD HOLDA PRGW R/W D31 – D0 A23 – A0 DMAADDR bus DMADA T A bus DADDR2 bus DADDR1 bus DDA T A bus P ADDR bus PDA T A bus Program counter/ instruction register CPU DMA controller 32 24.
Memory Organization 2-17 Architectural Overview 2.5.2 Memory Addressing Modes The ’C3x supports a base set of general-purpose instructions as well as arithmetic- intensive instructions that are particularly suited for digital signal processing and other numeric-intensive applications.
Internal Bus Operation 2-18 2.6 Internal Bus Operation Muc h of t he ’ C3x ’s hig h pe rf or ma nce i s d ue to int er na l bu sin g an d parallelism.
External Memory Interface 2-19 Architectural Overview 2.7 External Memory Interface The ’C30 provides two external interfaces: the primary bus and the expansion bus. The ’C31 provides one external interface: the primary bus. The ’C32 pro - vides one enhanced external interface with three independent multi-function strobes.
External Memory Interface 2-20 2.7.2 TMS320C32 8-, 16-, and 32-Bit Data Memory The ’C32 external memory interface can load and store 8-, 16-, or 32-bit quanti- ties into external memory and convert them into an internally-equivalent 32-bit representation.
Interrupts 2-21 Architectural Overview 2.8 Interrupts The ’C3x supports four external interrupts (INT3–INT0 ), a number of internal interrupts, and a nonmaskable external RESET signal.
Peripherals 2-22 2.9 Peripherals All ’C3x peripherals are controlled through memory-mapped registers on a dedi- cated peripheral bus. This peripheral bus is composed of a 32-bit data bus and a 24-bit address bus. This peripheral bus permits straightforward communica- tion to the peripherals.
Peripherals 2-23 Architectural Overview 2.9.1 Timers The two timer modules are general-purpose 32-bit timer/event counters with two signaling modes and internal or external clocking. They can signal internally to the ’C3x or externally to the outside world at specified intervals or they can count external events.
Direct Memory Access (DMA) 2-24 2.10 Direct Memory Access (DMA) The on-chip DMA controller can read from or write to any location in the memory map without interfering with the CPU operation. The ’C3x can inter- face to slow , external memories and peripherals without reducing throughput to the CPU.
Direct Memory Access (DMA) 2-25 Architectural Overview Figure 2–10. DMA Controller DMAADDR bus DMADA T A bus DMA controller Global-control register Source-address register Destination-address regist.
TMS320C30, TMS320C31, and TMS320C32 Differences 2-26 2.1 1 TMS320C30, TMS320C31, and TMS320C32 Differences T able 2–2 shows the major differences between the ’C32, ’C31, and the ’C30 devices.
TMS320C30, TMS320C31, and TMS320C32 Differences 2-27 Architectural Overview T able 2–2. Feature Set Comparison Feature ’C30 ’C31 ’C32 External bus T wo buses: Primary bus: 32-bit data 24-bit a.
3-1 CPU Registers The central processing unit (CPU) register file contains 28 registers that can be operated on by the multiplier and arithmetic logic unit (ALU). Included in the register file are the auxiliary registers, extended-precision registers, and index registers.
CPU Multiport Register File 3-2 3.1 CPU Multiport Register File The ’C3x provides 28 registers in a multiport register file that is tightly coupled to the CPU. The program counter (PC) is not included in the 28 registers. All of these registers can be operated on by the multiplier and the ALU and can be used as general-purpose 32-bit registers.
CPU Multiport Register File 3-3 CPU Registers The registers also have some special functions for which they are particularly appropriate. For example, the eight extended-precision registers are especially suited for maintaining extended-precision floating-point results.
CPU Multiport Register File 3-4 3.1.2 Auxiliary Registers (AR7–AR0) The CPU can access the eight 32-bit auxiliary registers (AR7–AR0), and the two auxiliary register arithmetic units (ARAUs) can modify them. The primary function of the auxiliary registers is the generation of 24-bit addresses.
CPU Multiport Register File 3-5 CPU Registers 3.1.7 Status (ST) Register The status (ST) register contains global information about the state of the CPU. Operations usually set the condition flags of the status register according to whether the result is 0, negative, etc.
CPU Multiport Register File 3-6 T able 3–2. Status Register Bits Bit Name Reset V alue Name Description C 0 Carry flag Carry condition flag V 0 Overflow flag Overflow condition flag Z 0 Zero flag Ze.
CPU Multiport Register File 3-7 CPU Registers T able 3–2. Status Register Bits (Continued) Bit Name Description Name Reset V alue CF 0 Cache freeze Enables or disables the instruction cache Set CF = 1 to freeze the cache (cache is not updated), including LRU stack manipulation.
CPU Multiport Register File 3-8 T able 3–2. Status Register Bits (Continued) Bit Name Description Name Reset V alue PRGW Dependent on PRGW pin level Program width status (‘C32 only) Indicates the status of the external input PRGW pin. When the signal of the PRGW pin is high, the PRGW status bit is set to 1, indicating a 16-bit memory width.
CPU Multiport Register File 3-9 CPU Registers 3.1.8 CPU/DMA Interrupt-Enable (IE) Register The CPU/DMA interrupt-enable (IE) register of the ’C30, ’C31, and ’C32 are 32-bit registers (see Figure 3–5 and Figure 3–6). The CPU interrupt-enable bits are in locations 10 – 0 for ’C30 and ’C31 devices, and 1 1 – 0 for ’C32 devices.
CPU Multiport Register File 3-10 T able 3–3. IE Bits and Functions Abbreviation Reset V alue Description EINT0 (CPU) 0 CPU external interrupt 0 enable EINT1 (CPU) 0 CPU external interrupt 1 enable E.
CPU Multiport Register File 3-1 1 CPU Registers T able 3–3. IE Bits and Functions(Continued) Abbreviation Description Reset V alue ETINT0 (DMA) 0 DMA timer0 interrupt enable (’C30 and ’C31) ETIN.
CPU Multiport Register File 3-12 Figure 3–7. TMS320C30 CPU Interrupt Flag (IF) Register XINT1 RINT1 yy yy 7 11 15–12 31–16 xx 10 DINT 9 TINT1 8 TINT0 5 RINT0 4 XINT0 3 INT3 2 INT2 1 INT1 60 INT0.
CPU Multiport Register File 3-13 CPU Registers T able 3–4. IF Bits and Functions Bit Name Reset V alue Function INT0 0 External interrupt 0 flag INT1 0 External interrupt 1 flag INT2 0 External inte.
CPU Multiport Register File 3-14 3.1.9.1 Interrupt-Trap T able Pointer (ITTP) Similar to the rest of the ‘C3x device family , the ’C32’ s reset vector location remains at address 0.
CPU Multiport Register File 3-15 CPU Registers Figure 3–1 1. Interrupt and T rap V ector Locations EA (ITTP) + 3Fh EA (ITTP) + 3Eh EA (ITTP) + 3Dh EA (ITTP) + 3Ch EA (ITTP) + 3Bh EA (ITTP) + 20h TRA.
CPU Multiport Register File 3-16 3.1.10 I/O Flag (IOF) Register The I/O flag (IOF) register is shown in Figure 3–12 and controls the function of the dedicated external pins, XF0 and XF1. These pins can be configured for input or output. The pins can also be read from and written to.
CPU Multiport Register File 3-17 CPU Registers 3.1.1 1 Repeat-Counter (RC) and Block-Repeat (RS, RE) Registers The repeat-counter (RC) register is a 32-bit register that specifies the number of times a block of code is to be repeated when a block repeat is performed.
Other Registers 3-18 3.2 Other Registers 3.2.1 Program-Counter (PC) Register The program counter (PC) is a 32-bit register containing the address of the next instruction fetch. While the program-counter register is not part of the CPU register file, it can be modified by instructions that modify the program flow .
Reserved Bits and Compatibility 3-19 CPU Registers 3.3 Reserved Bits and Compatibility T o retain compatibility with future members of the ’C3x family of microprocessors, reserved bits that are read as 0 must be written as 0. Y ou must not modify the current value of a reserved bit that has an undefined value.
4-1 Memory and the Instruction Cache The ’C3x provides a total memory space of 16M (million) 32-bit words that contain program, data, and I/O space. T wo RAM blocks of 1K 32 bits each (available on .
Memory 4-2 4.1 Memory The ’C3x accesses a total memory space of 16M (million) 32-bit words of pro- gram, data, and I/O space and allows tables, coefficients, program code, or data to be stored in either RAM or ROM. In this way , you can maximize memory usage and allocate memory space as desired.
Memory 4-3 Memory and the Instruction Cache Microcomputer Mode In microcomputer mode, the 4K on-chip ROM is mapped into locations 0h–0FFFh. There are 192 locations (0h–0BFh) within this block for interrupt vectors, trap vectors, and a reserved space (’C30).
Memory 4-4 Figure 4–1. TMS320C30 Memory Maps Reset, interrupt, trap vectors, and reserved locations (64) (external STRB active) 0h 03Fh 040h External STRB active (8.
Memory 4-5 Memory and the Instruction Cache 4.1.1.2 TMS320C31 Memory Map The memory map depends on whether the processor is running in micropro- cessor mode (MCBL/MP = 0) or microcomputer mode (MCBL/MP = 1). The memory maps for these modes are similar (see Figure 4–2 on page 4-6).
Memory 4-6 Figure 4–2. TMS320C31 Memory Maps Reset, interrupt, trap vectors, and reserved locations (64) (external STRB active) 0h 03Fh 040h External STRB active (8.
Memory 4-7 Memory and the Instruction Cache 4.1.1.3 TMS320C32 Memory Map The memory map depends on whether the processor is running in micropro- cessor mode (MCBL/MP = 0) or microcomputer mode (MCBL/MP = 1). The memory maps for these modes are similar (see Figure 4–3 on page 4-8 ).
Memory 4-8 Figure 4–3. TMS320C32 Memory Maps External memory STRB1 active (7.168M words) External memory STRB1 active (7.168M words) Boot 3 External memory STRB0 active (512K words) Microprocessor m.
Memory 4-9 Memory and the Instruction Cache 4.1.2 Peripheral Bus Memory Map The following sections describe the peripherial bus memory maps for the ’C30, ’C31, and ’C32. 4.1.2.1 TMS320C30 Peripheral Bus Memory Map The ’C30 memory-mapped peripheral registers are located starting at address 808000h.
Memory 4-10 Figure 4–4. TMS320C30 Peripheral Bus Memory-Mapped Registers Serial port 1 data transmit 808064h Primary-bus control 808060h Expansion-bus control 80804Ch Serial port 0 data receive 8080.
Memory 4-1 1 Memory and the Instruction Cache 4.1.2.2 TMS320C31 Peripheral Bus Memory Map The ’C31 memory-mapped peripheral registers are located starting at address 808000h. Figure 4–5 shows the peripheral bus memory map. The shaded blocks are reserved.
Memory 4-12 4.1.2.3 TMS320C32 Peripheral Bus Memory Map The ’C32’s memory-mapped peripheral and external-bus control registers are located starting at address 808000h, as shown in Figure 4–6 on page 4-13.
Memory 4-13 Memory and the Instruction Cache Figure 4–6. TMS320C32 Peripheral Bus Memory-Mapped Registers 8097FFh 808068h STRB1 bus control 808064h STRB0 bus control 808060h IOSTRB bus control 80804.
Reset/Interrupt/T rap V ector Map 4-14 4.2 Reset/Interrupt/T rap V ector Map The addresses for the reset, interrupt, and trap vectors are 00h–3Fh, as shown in Figure 4–7 and Figure 4–8. The reset vector contains the address of the reset routine.
Reset/Interrupt/T rap V ector Map 4-15 Memory and the Instruction Cache Figure 4–7. Reset, Interrupt, and T rap V ector Locations for the TMS320C30 Microprocessor Mode RESET 00h INT0 01h INT1 02h IN.
Reset/Interrupt/T rap V ector Map 4-16 Figure 4–8. R e s e t , I n t e r r u p t , a n d T ra p V e ct o r L o c a t i o n s f or t h e T M S 320C31 Microprocessor Mode 00h RESET 01h INT0 02h INT1 0.
Reset/Interrupt/T rap V ector Map 4-17 Memory and the Instruction Cache Figure 4–9. Interrupt and T rap Branch Instructions for the TMS320C31 Microcomputer Mode 809FC1h INT0 809FC2h INT1 809FC3h INT.
Reset/Interrupt/T rap V ector Map 4-18 Figure 4–10. Interrupt and T rap V ector Locations for TMS320C32 EA (ITTP) + 3Fh EA (ITTP) + 3Eh EA (ITTP) + 3Dh EA (ITTP) + 3Ch EA (ITTP) + 3Bh EA (ITTP) + 20.
Instruction Cache 4-19 Memory and the Instruction Cache 4.3 Instruction Cache A 64 × 32-bit instruction cache speeds instruction fetches and lowers system cost by caching program fetches from external memory . The instruction cache allows the use of slow , external memories while still achieving single-cycle access performances.
Instruction Cache 4-20 Figure 4–12. Instruction-Cache Architecture Segment start address registers Segment words LRU Stack SSA register 0 Segment word 0 Segment word 1 Segment word 30 Segment word 3.
Instruction Cache 4-21 Memory and the Instruction Cache 4.3.2 Instruction-Cache Algorithm When the ’C3x requests an instruction word from external memory , one of two possible actions occurs: a cache hit or a cache miss .
Instruction Cache 4-22 Only instructions may be fetched from the program cache. All reads and writes of data in memory bypass the cache. Program fetches from internal memory do not modify the cache and do not generate cache hits or misses. The pro- gram cache is a single-access memory block.
Instructions may be fetched before cache is enabled or frozen. Cache cleared Instructions may be fetched before cache cleared. Instruction Cache 4-23 Memory and the Instruction Cache T able 4–1.
5-1 Data Formats and Floating-Point Operation In the ’C3x architecture, data is organized into three fundamental types: integer , unsigned integer , and floating-point. The terms integer and signed integer are equivalent. The ’C3x supports short and single-precision formats for signed and unsigned integers.
Integer Formats 5-2 5.1 Integer Formats The ’C3x supports two integer formats: a 16-bit short-integer format and a 32-bit single-precision integer format. Note: When extended-precision registers are used as integer operands, only bits 31–0 are used; bits 39–32 remain unchanged.
Unsigned-Integer Formats 5-3 Data Formats and Floating-Point Operation 5.2 Unsigned-Integer Formats The ’C3x supports two unsigned-integer formats: a 16-bit short format and a 32-bit single-precision format. Note: In extended-precision registers, the unsigned-integer operands use only bits 31– 0; bits 39–32 remain unchanged.
Floating-Point Formats 5-4 5.3 Floating-Point Formats The ’C3x supports four floating-point formats: A short floating-point format for immediate floating-point operands, consisting of a 4-bit expone.
Floating-Point Formats 5-5 Data Formats and Floating-Point Operation The exponent field is a 2s-complement number that determines the factor of 2 by which the number is multiplied. Essentially , the exponent field shifts the binary point in the mantissa.
Floating-Point Formats 5-6 The following examples illustrate the range and precision of the short floating- point format: Most positive: x = (2 – 2 –1 1 ) × 2 7 = 2.5594 × 10 2 Least positive: x = 1 × 2 –7 = 7.8125 × 10 –3 Least negative: x = (–1– 2 –1 1 ) × 2 –7 = –7.
Floating-Point Formats 5-7 Data Formats and Floating-Point Operation The following examples illustrate the range and precision of the ‘C32 short floating-point format for external 16-bit data: Most positive: x = (2–2 –8 ) 2 127 = 3.3961775 10 38 Least positive x = 1 2 –127 = 5.
Floating-Point Formats 5-8 Y ou must use the following reserved values to represent 0 in the single-precision floating-point format: e = – 128 s =0 f =0 The following examples illustrate the range and precision of the single-precision floating-point format: Most positive: x = (2 – 2 –2 3 ) × 2 127 = 3.
Floating-Point Formats 5-9 Data Formats and Floating-Point Operation The following examples illustrate the range and precision of the extended- precision floating-point format: Most positive: x = (2 – 2 –2 3 ) × 2 127 = 3.4028234 × 10 38 Least positive: x = 1 × 2 –127 = 5.
Floating-Point Formats 5-10 Rewrite the mantissa as: Mantissa 1 0 . 1 0 1 0 0 0 0 0 0 0 0 Step 3: Shift the decimal point of the mantissa according to the value of the exponent. If the exponent is positive, shift the binary point to the right by the value of the exponent.
Floating-Point Formats 5-1 1 Data Formats and Floating-Point Operation Example 5–2. Negative Number 0 1 C 0 0 0 0 0 Hex value 0000 0001 1100 0000 0000 0000 0000 0000 Binary value Exponent = 0000 0001 2 = 1 Sign = 1 Fraction = .10000 2 Value = 10.1 2 × 2 1 = 101 2 .
Floating-Point Formats 5-12 5.3.6 Conversion Between Floating-Point Formats Floating-point operations assume several different formats for inputs and out- puts. These formats often require conversion from one floating-point format to another (for example, short floating-point format to extended-precision floating- point format).
Floating-Point Formats 5-13 Data Formats and Floating-Point Operation Figure 5–12. Converting from Single-Precision Floating-Point Format to Extended-Precision Floating-Point Format Single-precision.
Floating-Point Conversion (IEEE Std. 754) 5-14 5.4 Floating-Point Conversion (IEEE Std. 754) The ‘C3x floating-point format is not compatible with the IEEE standard 754 format. The IEEE floating-point format uses sign-magnitude notation for the mantissa, and the exponent is biased by 127.
Floating-Point Conversion (IEEE Std. 754) 5-15 Data Formats and Floating-Point Operation Figure 5–15. TMS320C3x Single-Precision 2s-Complement Floating-Point Format e f 31 23 22 0 24 s Note: Same format as for the ’C4x In comparison, Figure 5–15 shows the the ‘C3x 2s-complement floating-point format.
Floating-Point Conversion (IEEE Std. 754) 5-16 Case 1 maps the IEEE positive NaNs and positive infinity to the single-preci- sion 2s-complement most positive number .
Floating-Point Conversion (IEEE Std. 754) 5-17 Data Formats and Floating-Point Operation 5.4.1.1 IEEE-to-TMS320C3x Floating-Point Format Conversion Example 5–4 shows the fast conversion from IEEE to ’C3x floating-point format. It properly handles the general case when 0 < e < 255, and also handles 0s (that is, e = 0 and f = 0).
Floating-Point Conversion (IEEE Std. 754) 5-18 Example 5–4. IEEE-to-TMS320C3x Conversion (Fast V ersion) (Continued) * NOTE: SINCE THE STACK POINTER SP IS USED, MAKE SURE TO * INITIALIZE IT IN THE CALLING PROGRAM. * * * CYCLES: 12 (WORST CASE) WORDS: 12 * .
Floating-Point Conversion (IEEE Std. 754) 5-19 Data Formats and Floating-Point Operation Example 5–5. IEEE-to-TMS320C3x Conversion (Complete V ersion) * TITLE IEEE TO TMS320C3x CONVERSION (COMPLETE VERSION) * * * SUBROUTINE FMIEEE1 * * FUNCTION: CONVERSION BETWEEN THE IEEE FORMAT AND THE TMS320C3x * FLOATING-POINT FORMAT.
Floating-Point Conversion (IEEE Std. 754) 5-20 Example 5–5. IEEE-to-TMS320C3x Conversion (Complete V ersion) (Continued) * HANDLE NaN AND INFINITY TSTB *+AR1(7),R0 RETSNZ ; Return if NaN LDI R0,R0 L.
Floating-Point Conversion (IEEE Std. 754) 5-21 Data Formats and Floating-Point Operation 5.4.2 Conver ting 2s-Complement TMS320C 3x Floating-Point For mat to IEEE Form at This conversion is performed according to the following table: T able 5–2.
Floating-Point Conversion (IEEE Std. 754) 5-22 5.4.2.1 TMS320C3x-to-IEEE Floating-Point Format Conversion The vast majority of the numbers represented by the ’C3x floating-point format are covered by the general IEEE format and the representation of 0s.
Floating-Point Conversion (IEEE Std. 754) 5-23 Data Formats and Floating-Point Operation Example 5–6. TMS320C3x-to-IEEE Conversion (Fast V ersion) (Continued) * CYCLES: 14 (WORST CASE) WORDS: 15 * .
Floating-Point Conversion (IEEE Std. 754) 5-24 Example 5–7. TMS320C3x-to-IEEE Conversion (Complete V ersion) * * TITLE TMS320C3x TO IEEE CONVERSION (COMPLETE VERSION) * * * SUBROUTINE TOIEEE1 * * * FUNCTION: CONVERSION BETWEEN THE TMS320C3x FORMAT AND THE IEEE * FLOATING-POINT FORMAT.
Floating-Point Conversion (IEEE Std. 754) 5-25 Data Formats and Floating-Point Operation Example 5–7. TMS320C3x-to-IEEE Conversion (Complete V ersion) (Continued) * TOIEEE1 LDF R0,R0 ; Determine the.
Floating-Point Multiplication 5-26 5.5 Floating-Point Multiplication A floating-point number α can be written in floating-point format as in the following formula, where α ( man ) is the mantissa an.
Floating-Point Multiplication 5-27 Data Formats and Floating-Point Operation If c ( exp ) has overflowed (step 1 1) in the positive direction, then step 14 sets c ( exp ) to the most positive extended-precision format value.
Floating-Point Multiplication 5-28 Figure 5–16. Flowchart for Floating-Point Multiplication α ( man ) b ( man ) α ( exp ) b ( exp ) (1) (2) Multiply mantissas Add exponents c ( man ) = α ( man ) .
Floating-Point Multiplication 5-29 Data Formats and Floating-Point Operation Example 5–8 through Example 5–12 illustrate how floating-point multiplication is performed on the ’C3x. For these examples, the implied most significant nonsign bit is made explicit.
Floating-Point Multiplication 5-30 Example 5–9. Floating-Point Multiply (Both Mantissas = 1.5) Let: α = 1.5 × 2 α ( exp ) = 01.0000000000000000000000 × 2 α ( exp ) b = 1.5 × 2 b ( exp ) = 01.0000000000000000000000 × 2 b ( exp ) Where: a and b are both represented in binary form according to the single-preci- sion floating-point format.
Floating-Point Multiplication 5-31 Data Formats and Floating-Point Operation Example 5–1 1. Floating-Point Multiply Between Positive and Negative Numbers Let: α = 1.0 x 2 α ( exp ) = 01.00000000000000000000000 x 2 α ( exp ) b = –2.0 x 2 b ( exp ) = 10.
Floating-Point Addition and Subtraction 5-32 5.6 Floating-Point Addition and Subtraction In floating-point addition and subtraction, two floating-point numbers α and b can be defined as: α = α ( ma.
Floating-Point Addition and Subtraction 5-33 Data Formats and Floating-Point Operation Figure 5–17. Flowchart for Floating-Point Addition α ( man ) b ( man ) α ( exp ) b ( exp ) (3) (2) Align mant.
Floating-Point Addition and Subtraction 5-34 The following examples describe the floating-point addition and subtraction operations. It is assumed that the data is in the extended-precision floating- point format. Example 5–13. Floating-Point Addition In the case of two normalized numbers to be summed, let α = 1.
Floating-Point Addition and Subtraction 5-35 Data Formats and Floating-Point Operation Example 5–14. Floating-Point Subtraction A subtraction is performed in this example. Let: α = 01.0000000000000000000000000000001 × 2 0 b = 01.0000000000000000000000000000000 × 2 0 The operation performed is α – b .
Floating-Point Addition and Subtraction 5-36 Example 5–16. Floating-Point Addition/Subtraction With Floating-Point 0 When floating-point addition and subtraction are performed with a floating- point.
Normalization Using the NORM Instruction 5-37 Data Formats and Floating-Point Operation 5.7 Normalization Using the NORM Instruction The NORM instruction normalizes an extended-precision floating-point number that is assumed to be unnormalized (see Example 5–17 ).
Normalization Using the NORM Instruction 5-38 Figure 5–18. Flowchart for NORM Instruction Operation T est for special cases of c ( man ) c ( exp ) = –128 (1) α ( man ) = 0 T est for special cases.
Rounding (RND Instruction) 5-39 Data Formats and Floating-Point Operation 5.8 Rounding (RND Instruction) The RND instruction rounds a number from the extended-precision floating- point format to the single-precision floating-point format. Rounding is similar to floating-point addition.
Rounding (RND Instruction) 5-40 Figure 5–19. Flowchart for Floating-Point Rounding by the RND Instruction T est for special cases of c ( man ) c ( exp ) = –128 c ( man ) = 0 T est for special case.
Floating-Point to Integer Conversion (FIX Instruction) 5-41 Data Formats and Floating-Point Operation 5.9 Floating-Point to Integer Conversion (FIX Instruction) Using the FIX instruction, you can convert an extended-precision floating- point number to a single-precision integer in a single cycle.
Floating-Point to Integer Conversion (FIX Instruction) 5-42 Figure 5–20. Flowchart for Floating-Point to Integer Conversion by FIX Instruction T est for special cases of α ( exp ) α ( exp ) > 3.
Integer to Floating-Point Conversion (FLOA T Instruction) 5-43 Data Formats and Floating-Point Operation 5.10 Integer to Floating-Point Conversion (FLOA T Instruction) Integer to floating-point conversion, using the FLOA T instruction, allows single-precision integers to be converted to extended-precision floating-point numbers.
Fast Logarithms on a Floating-Point Device 5-44 5.1 1 Fast Logarithms on a Floating-Point Device The following TMS320C30/C40 function calculates the log base two of a number in about half the time of conventional algorithms. Furthermore, the method can easily be scaled for faster execution if less accuracy is desired.
Fast Logarithms on a Floating-Point Device 5-45 Data Formats and Floating-Point Operation N * l og 2 (mant_old) = EXP_new + log 2 (mant_new) log 2 (mant_old) = EXP_new / N + l og 2 (mant_new) / N This last equation shows that the logarithm of mant_old is indeed related to EXP_new .
Fast Logarithms on a Floating-Point Device 5-46 are equivalent to the seven MSBs of the logarithm. If the exponent cou ld ho ld all the bits needed for full accuracy , then it would be possible to continue the op - eration for all 24 bits of the mantissa.
Fast Logarithms on a Floating-Point Device 5-47 Data Formats and Floating-Point Operation When finished, the bits representing the finished logarithm are in a fixed-point notation and need to be scaled. This is done by using the FLOA T instruction fol- lowed by a multiplication by a constant scaling factor .
Fast Logarithms on a Floating-Point Device 5-48 Figure 5–23. Fast Logarithm for FFT Displays **************************************************************** * * FAST Logarithm for FFT displays * * .
6-1 Addressing Modes The ’C3x supports five groups of powerful addressing modes. Six types of addressing that allow data access from memory , registers, and the instruction word can be used within the groups. This chapter describes the operation, encoding, and implementation of the addressing modes.
Addressing T ypes 6-2 6.1 Addressing T ypes Y ou can access data from memory , registers, and the instruction word by using five types of addressing: Register addressing .
Register Addressing 6-3 Addressing Modes 6.2 Register Addressing In register addressing, a CPU register contains the operand, as shown in this example: ABSF R1 ; R1 = |R1| The syntax for the CPU registers, the assembler syntax, and the assigned function for those registers are listed in T able 6–1.
Direct Addressing 6-4 6.3 Direct Addressing In direct addressing, the data address is formed by the concatenation of the eight LSBs of the data-page pointer (DP) with the 16 LSBs of the instruction word (expr).
Indirect Addressing 6-5 Addressing Modes 6.4 Indirect Addressing Indirect addressing specifies the address of an operand in memory through the contents of an auxiliary register , optional displacements, and index registers as shown in Example 6–2. Only the 24 LSBs of the auxiliary registers and index registers are used in indirect addressing.
Indirect Addressing 6-6 Figure 6–2. Indirect Addressing Operand Encoding LSB MSB 5 bits mod ARn disp 3 bits 0, 5, or 8 bits Note: Auxiliary Register The auxiliary register (AR n ) is encoded in the .
Indirect Addressing 6-7 Addressing Modes T able 6–2. Indirect Addressing (a) Indirect addressing with displacement Mod Field Syntax Operation Description 00000 *+AR n ( disp ) addr = AR n + disp Wit.
Indirect Addressing 6-8 T able 6–2. Indirect Addressing (Continued) (c) Indirect addressing with index register IR1 Mod Field Syntax Operation Description 10000 *+ AR n (IR1) addr = AR n + IR1 With .
Indirect Addressing 6-9 Addressing Modes Example 6–3. Indirect Addressing With Predisplacement Add The address of the operand to fetch is the sum of an auxiliary register (AR n ) and the displacement ( disp ). The displacement is either an 8-bit unsigned integer contained in the instruction word or an implied value of 1.
Indirect Addressing 6-10 Example 6–5. Indirect Addressing With Predisplacement Add and Modify The address of the operand to fetch is the sum of an auxiliary register (AR n ) and the displacement ( disp ). The displacement is either an 8-bit unsigned integer contained in the instruction word or an implied value of 1.
Indirect Addressing 6-1 1 Addressing Modes Example 6–7. Indirect Addressing With Postdisplacement Add and Modify The address of the operand to fetch is the contents of an auxiliary register (AR n ). After the operand is fetched, the displacement ( disp ) is added to the auxiliary register .
Indirect Addressing 6-12 Example 6–9. Indirect Addressing With Postdisplacement Add and Circular Modify The address of the operand to fetch is the contents of an auxiliary register (AR n ). After the operand is fetched, the displacement ( disp ) is added to the contents of the auxiliary register using circular addressing.
Indirect Addressing 6-13 Addressing Modes Example 6–1 1. Indirect Addressing With Preindex Add The address of the operand to fetch is the sum of an auxiliary register (AR n ) and an index register (IR0 or IR1).
Indirect Addressing 6-14 Example 6–13. Indirect Addressing With Preindex Add and Modify The address of the operand to fetch is the sum of an auxiliary register (AR n ) and an index register (IR0 or IR1). After the data is fetched, the auxiliary register is updated with the generated address.
Indirect Addressing 6-15 Addressing Modes Example 6–15. Indirect Addressing With Postindex Add and Modify The address of the operand to fetch is the contents of an auxiliary register (AR n ). After the operand is fetched, the index register (IR0 or IR1) is added to the auxiliary register .
Indirect Addressing 6-16 Example 6–17. Indirect Addressing With Postindex Add and Circular Modify The address of the operand to fetch is the contents of an auxiliary register (AR n ). After the operand is fetched, the index register (IR0 or IR1) is added to the auxiliary register .
Indirect Addressing 6-17 Addressing Modes Example 6–19. Indirect Addressing With Postindex Add and Bit-Reversed Modify The address of the operand to fetch is the contents of an auxiliary register (AR n ). After the operand is fetched, the index register (IR0) is added to the auxiliary register .
Immediate Addressing 6-18 6.5 Immediate Addressing In immediate addressing, the operand is a 16-bit (short) or 24-bit (long) immediate value contained in the 16 or 24 LSBs of the instruction word (expr).
PC-Relative Addressing 6-19 Addressing Modes 6.6 PC-Relative Addressing Program counter (PC)-relative addressing is used for branching. It adds the contents of the 16 or 24 LSBs of the instruction word to the PC register . The assembler takes the src (a label or address) specified by the user and generates a displacement.
PC-Relative Addressing 6-20 Figure 6–3. Encoding for 24-Bit PC-Relative Addressing Mode (a) BR, BRD: unconditional branches (standard and delayed) 31 25 24 23 0 0 1 1 0 0 0 0 0 Displacement (b) CALL.
Circular Addressing 6-21 Addressing Modes 6.7 Circular Addressing Many DSP algorithms, such as convolution and correlation, require a circular buffer in memory . In convolution and correlation, the circular buffer acts as a sliding window that contains the most recent data to process.
Circular Addressing 6-22 Figure 6–6. Logical and Physical Representation of Circular Buffer after Writing Eight Values Start End a) Logical representation value 6 value 7 value 2 value 6 value 2 val.
Circular Addressing 6-23 Addressing Modes In circular addressing, index r ef e rs t o t h e K L S B s ( f r o m t h e K - b i t boundary criteria) of the auxiliary register selected, and step is the quantity being added to or subtracted from the auxiliary register .
Circular Addressing 6-24 Example 6–24. Circular Addressing *AR0 ++ (5)% ; AR0 = 0 (0 value) *AR0 ++ (2)% ; AR0 = 5 (1st value) *AR0 – – (3)% ; AR0 = 1 (2nd value) *AR0++(6)% ; AR0 = 4 (3rd value.
Circular Addressing 6-25 Addressing Modes Example 6–25. FIR Filter Code Using Circular Addressing * Impulse Response .sect ”Impulse_Resp” H .float 1.0 .float 0.99 .float 0.95 . . . .float 0.1 * Input Buffer X .usect ”Input_Buf”,128 .data HADDR .
Bit-Reversed Addressing 6-26 6.8 Bit-Reversed Addressing The ’C3x can implement fast Fourier transforms (FFT) with bit-reversed ad- dressing. Whenever data in increasing sequence order is transformed by an FFT , the resulting data is presented in bit-reversed order .
Bit-Reversed Addressing 6-27 Addressing Modes Example 6–26. Bit-Reversed Addressing *AR2++(IR0)B ; AR2 = 0110 0000 (0th value) *AR2++(IR0)B ; AR2 = 0110 1000 (1st value) *AR2++(IR0)B ; AR2 = 0110 01.
Aligning Buffers With the TMS320 Floating-Point DSP Assembly 6-28 6.9 Aligning Buffers With the TMS320 Floating-Point DSP Assembly Language T ools T o align buffers to a K-bit boundary , you can use the .
System and User Stack Management 6-29 Addressing Modes 6.10 System and User Stack Management The ’C3x provides a dedicated system-stack pointer (SP) for building stacks in memory . The auxiliary registers can also be used to build a variety of more general linear lists.
System and User Stack Management 6-30 6.10.2 Stacks Stacks can be built from low to high memory or high to low memory . T wo cases for each type of stack are shown. Stacks can be built using the preincrement/ decrement and postincrement/decrement modes of modifying the auxiliary registers (AR).
System and User Stack Management 6-31 Addressing Modes Figure 6–1 1. Implementations of Low-to-High Memory Stacks T op of stack Low memory High memory (Free) Bottom of stack AR n T op of stack Low memory High memory (Free) Bottom of stack Case 3 Case 4 AR n .
7-1 Program Flow Control The TMS320C3x provides a complete set of constructs that facilitate software and hardware control of the program flow . Software control includes repeats, branches, calls, traps, and returns. Hardware control includes reset operation, interrupts, and power management.
Repeat Modes 7-2 7.1 Repeat Modes The repeat modes of the ’C3x can implement zero-overhead looping. For many algorithms, most execution time is spent in an inner kernel of code. Using the repeat modes allows these time-critical sections of code to be executed in the shortest possible time.
Repeat Modes 7-3 Program Flow Control 7.1.1 Repeat-Mode Control Bits T wo bits are important to the operation of RPTB and RPTS: RM bit. The repeat-mode (RM) flag bit in the status register specifies whether the processor is running in the repeat mode.
Repeat Modes 7-4 Example 7–1. Repeat-Mode Control Algorithm if RM == 1 ; If in repeat mode (RPTB or RPTS) if S == 1 ; If RPTS if first time through ; If this is the first fetch fetch instruction fro.
Repeat Modes 7-5 Program Flow Control All block repeats initiated by RPTB can be interrupted. When RPTB src (source) instruction executes, it performs the following sequence: 1) Load the start address of the block into repeat-start-address register (RS).
Repeat Modes 7-6 The RPTS instruction loads all registers and mode bits necessary for the opera- tion of the single-instruction repeat mode. Step 1 loads the start address of the block into RS. Step 2 loads the end address into the RE (end address of the block).
Repeat Modes 7-7 Program Flow Control Example 7–4. Incorrectly Placed Delayed Branch LDI 15,RC ; Load repeat counter with 15 RPTB ENDLOOP ; Execute block of code STLOOP ; from STLOOP to ENDLOOP 16 ; times . . . BRD OOPS ; This branch violates rule 2 ADDF MPYF ENDLOOP SUBF 7.
Repeat Modes 7-8 7.1.7 Nested Block Repeats Block repeats (RPTB) can be nested. Since the registers RS, RE, RC, and ST control the repeat-mode status, these registers must be saved and restored in order to nest block repeats.
Delayed Branches 7-9 Program Flow Control 7.2 Delayed Branches The ’C3x offers three main types of branching: standard, delayed, and condi- tional delayed. Standard branches empty the pipeline before performing the branch, ensuring correct management of the program counter and resulting in a ’C3x branch taking four cycles.
Delayed Branches 7-10 Example 7–6. Incorrectly Placed Delayed Branches B1: BD L1 NOP NOP B2: B L2 ; This branch is incorrectly placed. NOP NOP NOP . . . For faster execution, it might still be advantageous to use a delayed branch followed by NOP instructions by trading increased program size for faster speed.
Calls, T raps, and Returns 7-1 1 Program Flow Control 7.3 Calls, T raps, and Returns Calls and traps provide a means of executing a subroutine or function while providing a return to the calling routine. The CALL, CALL cond, and TRAP cond instructions store the value of the PC on the stack before changing the PC’s contents.
Calls, T raps, and Returns 7-12 RETI cond returns from traps or calls like the RETS cond , with the addition that RETI cond also sets the GIE bit of the status register , which enables all interrupts whose enabling bit is set to 1. The conditions for RETI cond are the same as for the CALL cond instruction.
Interlocked Operations 7-13 Program Flow Control 7.4 Interlocked Operations One of the most common parallel processing configurations is the sharing of global memory by multiple processors. For multiple processors to access this global memory and share data in a coherent manner , some sort of arbitration or handshaking is necessary .
Interlocked Operations 7-14 The LDFI and LDII instructions perform the following actions: 1) Simultaneously set XF0 to 0 and begin a read cycle. The timing of XF0 is similar to that of the address bus during a read cycle.
Interlocked Operations 7-15 Program Flow Control Note: Timing Diagrams for SIGI The timing diagrams for SIGI shown in the data sheets depict a zero wait state condition. Since the device idles until one cycle after XF1 is signaled, the data sheets show the XF1 signal sampled one H1/H3 cycle before setting the XF0 signal low .
Interlocked Operations 7-16 Example 7–8 shows the implementation of a busy-waiting loop. If location LOCK is the interlock for a critical section of code, and a nonzero means the lock is busy , the algorithm for a busy-waiting loop can be used as shown.
Interlocked Operations 7-17 Program Flow Control Figure 7–2. Multiple TMS320C3xs Sharing Global Memory Global memory Arbitration logic ’C3x #2 XF0 XF1 Local memory Local memory ’C3x #1 XF0 XF1 (.
Interlocked Operations 7-18 The ’C3x code for V(S) is shown in Example 7–10 ; code for P(S) is shown in Example 7–1 1 . Compare the code in Example 7–1 1 to the code in Example 7–9, which does not use semaphores.
Interlocked Operations 7-19 Program Flow Control Example 7–12. Code to Synchronize T wo TMS320C3x Devices at the Software Level N Code for ’C3x #2 Code for ’C3x #1 T ime O (W AIT) SIGI SIGI Synchronization occurs 7.
XF0 set as an output pin and XF1 set as an input pin XF1 sampled XF0 driven low and XF1 sampled XF0 pin driven high XF1 pin sampled XF0 pin driven low Interlocked Operations 7-20 Example 7–13.
Reset Operation 7-21 Program Flow Control 7.5 Reset Operation The ’C3x supports a nonmaskable external reset signal (RESET ), which is used to perform system reset. This section discusses the reset operation. At start-up, the state of the ’C3x processor is undefined.
Reset Operation 7-22 T able 7–3. TMS320C3x Pin Operation at Reset (Continued) Device Signal ‘C32 ‘C31 ‘C30 Operation at Reset HOLDA Reset has no effect PRGW Reset has no effect Expansion Bus I.
Reset Operation 7-23 Program Flow Control T able 7–3. TMS320C3x Pin Operation at Reset (Continued) Device Signal ‘C32 ‘C31 ‘C30 Operation at Reset DR1 Asynchronous reset; placed in high-impeda.
Reset Operation 7-24 T able 7–3. TMS320C3x Pin Operation at Reset (Continued) Device Signal ‘C32 ‘C31 ‘C30 Operation at Reset Emulation, T est, and Reserved EMU0 Undefined EMU1 Undefined EMU2 .
Reset Operation 7-25 Program Flow Control At system reset, the following additional operations are performed: The peripherals are reset. This is a synchronous operation. Peripheral reset is described in Chapter 12 , Peripherals . The external bus control registers are reset.
Interrupts 7-26 7.6 Interrupts The ’C3x supports multiple internal and external interrupts, which can be used for a variety of applications. Internal interrupts are generated by the DMA controller , timers, and serial ports. Four external maskable interrupt pins include INT0 – INT3.
Interrupts 7-27 Program Flow Control T able 7–4. Reset, Interrupt, and T rap-Vector Locations for the TMS320C30/ TMS320C31 Microprocessor Mode Address Name Function 00h RESET External reset signal i.
Interrupts 7-28 T able 7–5. Reset, Interrupt, and T rap-Branch Locations for the TMS320C31 Microcomputer Boot Mode Address Name Function 809FC1 INT0 External reset signal input 809FC2 INT1 External .
Interrupts 7-29 Program Flow Control 7.6.2 TMS320C32 Interrupt V ector T able Similarly to the rest of the ’C3x device family , the ’C32’s reset vector location remains at address 0. On the other hand, the interrupt and trap vectors are relocatable.
Interrupts 7-30 T able 7–6. Interrupt and T rap-V ector Locations for the TMS320C32 Address Name Function EA[ITTP] + 00h Reserved EA[ITTP] + 01h INT0 External interrupt on the INT0 pin EA[ITTP] + 02.
Interrupts 7-31 Program Flow Control 7.6.3 Interrupt Prioritization When two interrupts occur in the same clock cycle or when two previously received interrupts are waiting to be serviced, one interrupt is serviced before the other . The CPU handles this prioritization by servicing the interrupt with the least priority .
Interrupts 7-32 7.6.4 CPU Interrupt Control Bits Three CPU registers contain bits that control interrupt operation: Status (ST) register The CPU global interrupt-enable bit (GIE) located in the CPU status register (ST) controls all maskable CPU interrupts.
Interrupts 7-33 Program Flow Control Figure 7–5. IF Register Modification Correct Incorrect LDI @MASK, R0 LDI IF , R1 AND R0, IF AN D @M ASK, R1 LDI R1, IF Note: IF Register Load Priority If a load .
Interrupts 7-34 Figure 7–6. CPU Interrupt Processing DMA proceeds according to SYNC bits If enabled, interrupt is a DMA interrupt Clear interrupt flag DMA continues CPU starts executing ISR routine .
Interrupts 7-35 Program Flow Control If you wish to make the interrupt service routine interruptible, you can set the GIE bit to 1 after entering the ISR. The interrupt acknowledge (IACK) instruction can be used to signal externally that an interrupt has been serviced.
Interrupts 7-36 T able 7–8. Interrupt Latency Cycle Description Fetch Decode Read Execute 1 Recognize interrupt in single-cycle fetched (prog a + 1) instruction prog a + 1 prog a prog a–1 prog a–2 2 Clear GIE bit.
Interrupts 7-37 Program Flow Control Figure 7–7. Interrupt Logic Functional Diagram INTn To control section Internal interrupt set signal Interrupt flag (n) Internal interrupt processor Internal int.
DMA Interrupts 7-38 7.7 DMA Interrupts Interrupts can also trigger DMA read and write operations. This is called DMA synchronization. The DMA interrupt processing cycle is similar to that of the CPU.
DMA Interrupts 7-39 Program Flow Control 7.7.2 DMA Interrupt Processing Figure 7–8 shows the general flow of interrupt processing by the DMA coprocessor .
DMA Interrupts 7-40 7.7.3 CPU/DMA Interaction If the DMA is not using interrupts for synchronization of transfers, it is not affected by the processing of the CPU interrupts. Detected interrupts are responded to by the CPU and DMA on instruction fetch boundaries only .
DMA Interrupts 7-41 Program Flow Control 7.7.4 TMS320C3x Interrupt Considerations Give careful consideration to ’C3x interrupts, especially if you make modifications to the status register when the global interrupt-enable (GIE) bit is set. This can result in the GIE bit being erroneously set or reset as described in the following paragraphs.
DMA Interrupts 7-42 T able 7–9. Pipeline Operation with PUSH ST Cycle Description Fetch Decode Read Execute 1 NOP 2 LDI NOP 3 MPYI LDI NOP 4 Read location V_ADDR PUSH MPYI LDI NOP 5 Load AR1; recogn.
DMA Interrupts 7-43 Program Flow Control One solution is to use an instruction that is uninterruptible such as RPTS as follows to set the GIE: RPTS 0 AND 2000h, ST ; Set GIE=1 Use the following to res.
DMA Interrupts 7-44 7.7.5 TMS320C30 Interrupt Considerations The ’C30 silicon revisions earlier than 4.0 have two unique exceptions to the interrupt operation. This does not apply to ’C30 silicon revision 4.0 or greater , any ’C31 silicon, or any ’C32 silicon.
DMA Interrupts 7-45 Program Flow Control Insert two NOP instructions immediately before the TRAP cond instruction. One NOP is insufficient in some cases, as illustrated in the second bulleted item, above.
DMA Interrupts 7-46 ISR_n: PUSH ST ; PUSH DP ; Save registers PUSH R0 ; LDI 0, DP ; Clear Data-page Pointer LDI @DUMMY_INT, R0 ; If DUMMY_INT is 0 or positive, BNN ISR_n_START ; go to ISR_n_START STI DP, @DUMMY_INT ; Set DUMMY_INT = 0 POP R0 ; POP DP ; P O P S T ; Housekeeping, return from interrupt RETI ; ISR_n_START: .
T raps 7-47 Program Flow Control 7.8 T raps A trap is the equivalent of a software-triggered interrupt. In the ’C3x, traps and interrupts are treated identically , except in the way in which they are triggered.
T raps 7-48 The RETI cond instruction manipulates the status flags as shown in block (3) in Figure 7–10. RETI cond provides a return from a trap or interrupt.
Power Management Modes 7-49 Program Flow Control 7.9 Power Management Modes The following ’C3x devices have been enhanced by the addition of two power- down modes: IDLE2 and LOPOWER: ’C30 silicon version 7.0 or greater ’LC31 ’C31 silicon revision 5.
Power Management Modes 7-50 The interrupt service routine (ISR) must have been set up before placing the device in IDLE2 mode, because the instruction following the IDLE2 instruction is not executed until the RETI (return from interrupt) instruction is executed.
Power Management Modes 7-51 Program Flow Control Figure 7–12. Interrupt Response Timing After IDLE2 Operation 1st address V ector address Data ADDR INT0 Flag INT3 to INT0 INT3 to H1 H3 Fetch first instruction of service routing Interrupt vector read Clocks driven CLKIN 7.
Power Management Modes 7-52 Figure 7–13. LOPOWER Timing 32 CLKIN H1 H3 CLKIN LOPOWER read Figure 7–14. MAXSPEED Timing H1 H3 CLKIN MAXSPEED read 32 CLKIN.
8-1 Pipeline Operation Pipeline Operation T wo characteristics of the’C3x that contribute to its high performance are: Pipelining Concurrent I/O and CPU operation The following four functional units.
Perfect overlap Pipeline Structure 8-2 8.1 Pipeline Structure The following list describes the four major units of the ‘C3x pipeline structure and their functions: Fetch unit (F) Fetches the instruction words from memory and updates the program counter (PC).
Pipeline Structure 8-3 Pipeline Operation For ‘C30 and ‘C31, priorities from highest to lowest have been assigned to each of the functional units of the pipeline and to the DMA controller as follo.
Pipeline Conflicts 8-4 8.2 Pipeline Conflicts Pipeline conflicts in the ’C3x can be grouped into the following categories: Branch conflicts Branch conflicts involve most of those instructions or operations that read and/or modify the PC.
3P C Fetch held for new PC value Pipeline Conflicts 8-5 Pipeline Operation Example 8–1. Standard Branch BR THREE ; Unconditional branch MPYF ; Not executed ADD ; Not executed SUBF ; Not executed AND ; Not executed . . . THREE OR ; Fetched after BR is taken STI .
No execute delay 3P C Pipeline Conflicts 8-6 Example 8–2. Delayed Branch BRD THREE ; Unconditional delayed branch MPYF ; Executed ADD ; Executed SUBF ; Executed AND ; Not executed .
Decode/address generation held until AR write is completed ARs written Pipeline Conflicts 8-7 Pipeline Operation is loaded, and a different auxiliary register is used on the next instruction. Since the decode stage needs the result of the write to the auxiliary register , the decode of this second instruction is delayed two cycles.
Decode/address generation held until AR is read ARs read Pipeline Conflicts 8-8 In Example 8–4, two auxiliary registers are added together , with the result going to an extended-precision register . The next instruction uses a different auxiliary register as an address register .
Pipeline Conflicts 8-9 Pipeline Operation Memory pipeline conflicts consist of the following four types: Program wait A program fetch is prevented from beginning. Program fetch Incomplete A program fetch has begun but is not yet complete. Execute only An instruction sequence requires three CPU data accesses in a single cycle.
Fetch held until data access completes Data accessed Pipeline Conflicts 8-10 Example 8–5. Program Wait Until CPU Data Access Completes ADDF3 *AR0,*AR1,R0 FIX MPYF ADDF3 NEGB Pipeline Operation PC Fe.
2-cycle DMA access Pipeline Conflicts 8-1 1 Pipeline Operation Example 8–6. Program Wait Due to Multicycle Access ADDF ; code in internal memory MPY ; code in internal memory SUBF ; code in internal.
1 wait state required Pipeline Conflicts 8-12 Example 8–7. Multicycle Program Memory Fetches Pipeline Operation PC Fetch Decode Read Execute n MPYF — — — n+1 ADDF MPYF — — n+2 RDY SUBF ADDF MPYF — n+2 RDY SUBF (nop) ADDF MPYF n+3 ADDI SUBF (nop) ADDF Note: PC = program counter 8.
Write must complete before the two reads can complete 2 reads performed Pipeline Conflicts 8-13 Pipeline Operation Example 8–8. Single Store Followed by T wo Reads STF R 0,*AR1 ; R0 → *AR1 LDF *AR.
Read must wait until the writes are completed Writes performed Pipeline Conflicts 8-14 Example 8–9 shows a parallel store followed by a single load or read. Since two parallel stores are required, the next CPU data-memory read must wait one cycle before beginning.
XF1 = 1, read must wait XF1 = 0, read operation is complete Pipeline Conflicts 8-15 Pipeline Operation Example 8–10. Interlocked Load NOT R1,R0 LDII 300h,AR 2 ADDI *AR2,R2 CMPI R0,R2 Pipeline Operat.
write access 2-cycle external bus Pipeline Conflicts 8-16 Example 8–1 1. Busy External Port STF R0,@DMA1 LDF @DMA2,R0 Pipeline Operation PC Fetch Decode Read Execute n STF — — — n+1 LDF STF .
2-cycle external bus read access Pipeline Conflicts 8-17 Pipeline Operation Example 8–12. Multicycle Data Reads LDF @DMA,R0 Pipeline Operation PC Fetch Decode Read Execute n LDF — — — n+1 I LD.
PC store cycle Pipeline Conflicts 8-18 Example 8–13. Conditional Calls and T raps Pipeline Operation PC Fetch Decode Read Execute n CALL cond ——— n+1 I CALL cond —— n+1 (nop) (nop) CALL co.
ARs read Resolving Register Conflicts 8-19 Pipeline Operation 8.3 Resolving Register Conflicts If the auxiliary registers (AR7–AR0), the index registers (IR1–IR0), data-page pointer (DP), or stack pointer (SP) are accessed for any reason other than address generation, pipeline conflicts associated with the next memory access can occur .
AR2 read AR2 written Resolving Register Conflicts 8-20 Example 8–15. Write to an AR Followed by an AR for Address Generation Without a Pipeline Conflict LDI @TABLE,AR2 MPYF @VALUE,R1 ADDF R2,R1 MPYF.
DP read DP written Resolving Register Conflicts 8-21 Pipeline Operation Example 8–16. Write to DP Followed by a Direct Memory Read Without a Pipeline Conflict LDP TABLE_ADDR POP R0 LDF *–AR3(2),R1.
Memory Access for Maximum Performance 8-22 8.4 Memory Access for Maximum Performance If program fetches and data accesses are performed so that the resources being used cannot provide the necessary bandwidth, the pipeline is stalled until the data accesses are complete.
Memory Access for Maximum Performance 8-23 Pipeline Operation T able 8–2. One Program Fetch and T wo Data Accesses for Maximum Performance Case No. Primary Bus Accesses Accesses From Dual-Access Int.
Clocking Memory Accesses 8-24 8.5 Clocking Memory Accesses This section discusses the role of internal clock phases (H1 and H3) and how the ’C3x handles multiple-memory accesses. The previous section discusses the interaction between sequences of instructions; this section discusses the flow of data on an individual instruction basis.
Clocking Memory Accesses 8-25 Pipeline Operation See Chapter 6, Addressing Modes , for more information. As discussed in Chapter 7, the number of bus cycles for external memory accesses differs in some cases from the number of CPU execution cycles. For external reads, the number of bus cycles and CPU execution cycles is identical.
Clocking Memory Accesses 8-26 If both source operands are to be fetched from memory , then memory reads can occur in several ways: If both operands are located in internal memory , the src1 read is performed during H3 and the src2 read during H1, completing two memory reads in a single cycle.
2-cycle dummy load of src 2 R0, *AR6 until the store is complete actual read of src 2 and src 1 Clocking Memory Accesses 8-27 Pipeline Operation Example 8–17.
2-cycle store The read of src 2 cannot start until the store is complete 2-cycle read of src 1 and src 2 Clocking Memory Accesses 8-28 Example 8–18. Operand Swapping Alternative Switch the operands of the 3-operand instruction so that the internal read is performed first.
Clocking Memory Accesses 8-29 Pipeline Operation 8.5.2.3 Operations with Parallel Stores The next class of instructions includes every instruction that has a store in parallel with another instruction. Bits 31 and 30 for these instructions are equal to 1 1.
Clocking Memory Accesses 8-30 If dst1 and dst2 are both written to external memory , a single CPU cycle is still all that is necessary to complete the stores. In this case, four bus cycles are required. 1) In the first cycle, both dst1 and dst2 are written to the port, and the ex- ternal-bus access for dst1 begins.
9-1 TMS320C30 and TMS320C31 External-Memory Interface This chapter describes the ’C30 and ’C31 external-memory interface. See Chapter 10, Enhanced External-Memory Interface , for detailed information on the ’C32 external bus operation.
Overview 9-2 9.1 Overview The ’C30 provides two external interfaces: the primary bus and the expansion bus. The TMS320C31 provides one external interface: the primary bus. The primary bus consists of a 32-bit data bus, a 24-bit address bus, and a set of control signals.
Memory Interface Signals 9-3 TMS320C30 and TMS320C31 External-Memory Interface 9.2 Memory Interface Signals This section describes the differences between the ’C30 and ’C31 memory interface signals.
Memory Interface Signals 9-4 T able 9–1. Primary Bus Interface Signals Signal T ype † Description V alue After Reset Idle Status STRB O/Z Primary interface access strobe 1 1 R/W O/Z Specifies memo.
Memory Interface Signals 9-5 TMS320C30 and TMS320C31 External-Memory Interface T able 9–2. Expansion Bus Interface Signals Signal T ype † Description V alue After Reset Idle Status MSTRB O/Z Expan.
Memory Interface Signals 9-6 Figure 9–1. Memory-Mapped External Interface Control Registers Expansion-bus control (’C30 only) 808060h 808061h 808062h 808063h 808064h 808065h 808066h 808067h 808068.
Memory Interface Control Registers 9-7 TMS320C30 and TMS320C31 External-Memory Interface 9.3 Memory Interface Control Registers T wo memory interface control registers, the primary-bus control register and the expansion-bus control register , are described in this section.
Memory Interface Control Registers 9-8 T able 9–3. Primary-Bus Control Register Bits Abbreviation Reset V alue Name Description HOLDST 0 Hold status bit This bit signals whether the port is being held (HOLDST = 1) or is not being held (HOLDST = 0). This status bit is valid whether the port has been held through hardware or software.
Memory Interface Control Registers 9-9 TMS320C30 and TMS320C31 External-Memory Interface 9.3.2 Expansion-Bus Control Register The expansion-bus control register is a 32-bit register that contains control bits for the expansion bus (see Figure 9–3 and T able 9–4).
Programmable W ait States 9-10 9.4 Programmable W ait States The ’C3x has its own internal software-configurable ready-generation capability for each strobe. This software wait-state generator is controlled by configuring two bit fields in the primary or expansion bus interface control registers.
Programmable W ait States 9-1 1 TMS320C30 and TMS320C31 External-Memory Interface T able 9–5. Wait-State Generation Inputs Output SWW Bit Field /RDY ext /RDYwtcnt /RDYint Functional Description 00 0.
Programmable Bank Switching 9-12 9.5 Programmable Bank Switching Programmable bank switching allows you to switch between external memory banks without having to insert wait states externally due to memories that require several cycles to turn off. Bank switching is implemented on the primary bus only .
Programmable Bank Switching 9-13 TMS320C30 and TMS320C31 External-Memory Interface The ’C3x has an internal register that contains the MSBs (as defined by the BNKCMP field) of the last address used for a read or write over the primary inter - face. At reset, the register bits are set to 0.
Programmable Bank Switching 9-14 Figure 9–5. Bank-Switching Example H3 H1 STRB R/W A D RDY Read Read Read Extra cycle Note: After changing BNKCMP , up to three instructions are fetched before the change in the bank size occurs.
External Memory Interface Timing 9-15 TMS320C30 and TMS320C31 External-Memory Interface 9.6 External Memory Interface Timing This section discusses functional timing of operations on the primary bus and the expansion bus, the two independent parallel buses or the ’C3x devices.
External Memory Interface Timing 9-16 The (M)STRB signal is low for the active portion of both reads and writes. The active portion lasts one H1 cycle. Additionally , before and after the active portion ((M)STRB low) of writes only , there is a transition cycle of H1.
External Memory Interface Timing 9-17 TMS320C30 and TMS320C31 External-Memory Interface Figure 9–6. Read-Read-Write for (M)STRB = 0 H3 H1 (M)STRB (X)R/W (X)A (X)D (X)RDY Read Read Write data Note: (x) RDY is sampled low on rising edge of H1. Data is read next falling edge of H1.
External Memory Interface Timing 9-18 Figure 9–7 illustrates a write-write-read sequence for (M)STRB active and no wait states. The address and data written are held valid approximately one-half cycle after (M)STRB changes.
External Memory Interface Timing 9-19 TMS320C30 and TMS320C31 External-Memory Interface Figure 9–8 illustrates a read cycle with one wait state. Since (X)RDY = 1, the read cycle is extended. (M)STRB , (X)R/W , and (X)A are also extended one cycle. The next time (X)RDY is sampled, it is 0.
External Memory Interface Timing 9-20 Figure 9–9 illustrates a write cycle with one wait state. Since initially (X)RDY = 1, the write cycle is extended. (M)STRB , (X )R /W , and (X)A are extended one cycle. The next time (X)RDY is sampled, it is 0. Figure 9–9.
External Memory Interface Timing 9-21 TMS320C30 and TMS320C31 External-Memory Interface 9.6.2 Expansion-Bus I/O Cycles In contrast to primary bus and MSTRB cycles, IOSTRB reads and writes are both two cycles in duration (with no wait states) and exhibit the same timing.
External Memory Interface Timing 9-22 Figure 9–1 1 illustrates a read with one wait state when IOSTRB is active, and Figure 9–12 illustrates a write with one wait state when IOSTRB is active. For each wait state added, IOSTRB , XR/W , and XA are extended one clock cycle.
External Memory Interface Timing 9-23 TMS320C30 and TMS320C31 External-Memory Interface Figure 9–12. Write With One Wait State for IOSTRB = 0 H3 H1 XA XD XR/W IOSTRB XRDY Write data Extra cycle.
External Memory Interface Timing 9-24 Figure 9–13 through Figure 9–23 illustrate the various transitions between memory reads and writes, and I/O writes over the expansion bus.
External Memory Interface Timing 9-25 TMS320C30 and TMS320C31 External-Memory Interface Figure 9–14. Memory Read and I/O Read for Expansion Bus XRDY XD XA XR/W IOSTRB MSTRB H1 H3 I/O read Read I/O a.
External Memory Interface Timing 9-26 Figure 9–15. Memory Write and I/O Write for Expansion Bus H3 H1 XA XD XRDY MSTRB IOSTRB XR/W Memory address I/O address I/O write Memory write.
External Memory Interface Timing 9-27 TMS320C30 and TMS320C31 External-Memory Interface Figure 9–16. Memory Write and I/O Read for Expansion Bus H3 H1 XA XD XRDY MSTRB IOSTRB XR/W Memory address I/O.
External Memory Interface Timing 9-28 Figure 9–17. I/O Write and Memory Write for Expansion Bus H3 H1 XA XD XRDY MSTRB IOSTRB XR/W I/O address Memory address I/O write Memory write.
External Memory Interface Timing 9-29 TMS320C30 and TMS320C31 External-Memory Interface Figure 9–18. I/O Write and Memory Read for Expansion Bus H3 H1 XA XD XRDY MSTRB IOSTRB XR/W I/O address Memory.
External Memory Interface Timing 9-30 Figure 9–19. I/O Read and Memory Write for Expansion Bus I/O address Memory address Memory write XRDY XD XA XR/W IOSTRB MSTRB H1 H3 I/O read.
External Memory Interface Timing 9-31 TMS320C30 and TMS320C31 External-Memory Interface Figure 9–20. I/O Read and Memory Read for Expansion Bus Memory address I/O address XRDY XD XA XR/W IOSTRB MSTR.
External Memory Interface Timing 9-32 Figure 9–21. I/O Write and I/O Read for Expansion Bus I/O write XRDY XD XA XR/W IOSTRB MSTRB H1 H3 I/O read I/O address I/O address.
External Memory Interface Timing 9-33 TMS320C30 and TMS320C31 External-Memory Interface Figure 9–22. I/O Write and I/O Write for Expansion Bus I/O write I/O write XRDY XD XA XR/W IOSTRB MSTRB H1 H3 .
External Memory Interface Timing 9-34 Figure 9–23. I/O Read and I/O Read for Expansion Bus I/O read I/O read XRDY XD XA XR/W IOSTRB MSTRB H1 H3 I/O address I/O address.
External Memory Interface Timing 9-35 TMS320C30 and TMS320C31 External-Memory Interface Figure 9–24 and Figure 9–25 illustrate the signal states when a bus is inactive (after an IOSTRB or (M)STRB access, respectively). The strobes (STRB , MSTRB and IOSTRB ) an d (X )R / W ) go to 1.
External Memory Interface Timing 9-36 Figure 9–25. Inactive Bus States for STRB and MSTRB H3 H1 (X)A (X)D (X)R/W (M)STRB (X)RDY Write data (X)RDY ignored Bus inactive.
External Memory Interface Timing 9-37 TMS320C30 and TMS320C31 External-Memory Interface 9.6.3 Hold Cycles Figure 9–26 illustrates the timing for HOLD and HOLDA . HOLD is an external asynchronous input. There is a minimum of one cycle delay from the time when the processor recognizes HOLD = 0 until HOLDA = 0.
10-1 TMS320C32 Enhanced External Memory Interface The ’C32 external memory interface provides greater flexibility by improving the ’C3x core with several new features. This chapter describes these features and enhancements in detail. T opic Page 10.
TMS320C32 Memory Features 10-2 10.1 TMS320C32 Memory Features The ’C32 external memory interface includes the following features: One external pin, PRGW , configures the external-program-memory width to 16 or 32 bits.
TMS320C32 Memory Overview 10-3 TMS320C32 Enhanced External Memory Interface 10.2 TMS320C32 Memory Overview The following sections describe examples, control register setups, and restrictions necessary to fully understand the operation and functionality of the external memory interface.
TMS320C32 Memory Overview 10-4 IOSTRB can access 32-bit data from 32-bit wide memory . It does not have the flexibility of STRB0 and STRB1 since it is composed of a single signal: IOSTRB . IOSTRB bus cycles are dif ferent from those of STRB0 and STRB1 and are discussed in Section 10.
TMS320C32 Memory Overview 10-5 TMS320C32 Enhanced External Memory Interface The PRGW status bit field of the CPU status (ST) register reflects the setting of the PRGW pin. Figure 10–2 depicts all the bit fields of the CPU status (ST) register . Figure 10–2.
TMS320C32 Memory Overview 10-6 10.2.3.2 16- or 32-Bit Floating-Point Data T ypes The ’C32 supports 16- or 32-bit floating point data. For 16-bit floating-point reads, the eight MSBs are the signed exponent and the eight LSBs are the signed mantissa (see Section 5.
Configuration 10-7 TMS320C32 Enhanced External Memory Interface 10.3 Configuration T o access 8-, 16-, or 32-bit data (types) from 8-, 16-, or 32-bit wide memory , the memory interface of the ’C32 device uses either strobe STRB0 or STRB1 with four pins each.
Configuration 10-8 10.3.1.1 STRB0 Control Register The STRB0 control register (Figure 10–4) is a 32-bit register that contains the control bits for the portion of the external bus memory space that is mapped to STRB0 . The following table lists the register bits with the bit names and functions.
Configuration 10-9 TMS320C32 Enhanced External Memory Interface The instruction immediately preceding a change in the data-size or memory-width bit fields should not perform a multicycle store. Do not follow a change in the data-size or memory-width bit fields with a store instruction.
Configuration 10-10 T able 10–1 describes the bits in the STRBO , STRB1 , and the IOSTRB control registers. T able 10–1. STRB0 , STRB1 , and IOSTRB Control Register Bits Abbreviation Reset V alue Name Description HOLDST 0 Hold status bit This bit signals whether the port is being held (HOLDST = 1), or is not being held (HOLDST = 1).
Configuration 10-1 1 TMS320C32 Enhanced External Memory Interface T able 10–1. STRB0 , STRB1 , and IOSTRB Control Register Bits (Continued) Abbreviation Description Name Reset V alue Physical memory width 01 or 11 (STRB0 and STRB1 control registers only) Indicates the size of the physical memory connected to the device.
Configuration 10-12 T able 10–1. STRB0 , STRB1 , and IOSTRB Control Register Bits (Continued) Abbreviation Description Name Reset V alue Sign ext/ zero-fill 0 (STRB0 and STRB1 control registers only.
Configuration 10-13 TMS320C32 Enhanced External Memory Interface Figure 10–7. STRB Configuration STRB0_Bx STRB1_Bx STRB0_Bx STRB config STRB1_Bx 10.3.2 Using Physical Memory Width and Data-T ype Size Fields Consider a ’C32 connected to two banks of external memory .
Configuration 10-14 By setting the bit fields of the STRB0 bus control register with a physical- memory width of 32 bits and a data type size of 32 bits, the external address referring to the STRB0 location is identical to the internal address used by the ‘C32 CPU.
Programmable W ait States 10-15 TMS320C32 Enhanced External Memory Interface 10.4 Programmable W ait States The ’C3x has its own internal software-configurable ready-generation capability for each strobe. This software wait-state generator is controlled by configuring two fields in the primary or expansion bus interface control registers.
Programmable W ait States 10-16 T able 10–3. Wait-State Generation Inputs Output SWW Bit Field /RDY ext /RDYwtcnt /RDYint Functional Description 00 0 1 x x 0 1 W ait until external RDY is signaled 0.
Programmable Bank Switching 10-17 TMS320C32 Enhanced External Memory Interface 10.5 Programmable Bank Switching Programmable bank switching allows you to switch between external memory banks without having to insert wait states externally due to memories that require several cycles to turn off.
Programmable Bank Switching 10-18 The ’C3x has an internal register that contains the MSBs (as defined by the BNKCMP field) of the last address used for a read or write over the primary inter - face.
Programmable Bank Switching 10-19 TMS320C32 Enhanced External Memory Interface Note: After changing BNKCMP , up to three instructions are fetched before the change in bank size occurs.
32-Bit-Wide Memory Interface 10-20 10.6 32-Bit-Wide Memory Interface The ’C32 memory interface to 32-bit-wide external memory uses STRBx_B 3 through STRBx_B 0 pins as strobe-byte-enable pins as shown in Figure 10–10. In this manner , the ’C32 can read from, or write to, a single 32-, 16-, or 8-bit value from the external 32-bit-wide memory .
32-Bit-Wide Memory Interface 10-21 TMS320C32 Enhanced External Memory Interface T able 10–5. Strobe Byte-Enable for 32-Bit-Wide Memory With 8-Bit Data-T ype Size Internal A 1 Internal A 0 Active Strobe Byte Enable 0 0 STRBx_B0 0 1 STRBx_B1 1 0 STRBx_B2 1 1 STRBx_B3 Figure 10–1 1.
32-Bit-Wide Memory Interface 10-22 For example, reading from or writing to memory locations 90 4000h to 90 4004h involves the pins listed in T able 10–6.
32-Bit-Wide Memory Interface 10-23 TMS320C32 Enhanced External Memory Interface Figure 10–12. Fu n c t i onal Diagram for 16-Bit Data-T ype Size and 32-Bit External-Memory Widt h A22 A21 A20 A19 . . . A1 A0 CS I/O(7-0) ’C32 A 23 A 22 A 21 A 20 A 19 .
32-Bit-Wide Memory Interface 10-24 Case 3: 32-Bit-Wide Memory With 32-Bit Data-T ype Size When the data size is 32 bits, the ’C32 does not shift the internal address before presenting it to the external address pins. In this case, the memory interface copies the value of the internal address bus to the respective external- address pins.
32-Bit-Wide Memory Interface 10-25 TMS320C32 Enhanced External Memory Interface For example, reading or writing to memory locations 904000h to 904004h involves the pins listed in T able 10–9.
16-Bit-Wide Memory Interface 10-26 10.7 16-Bit-Wide Memory Interface The ’C32 memory interface to 16-bit-wide external memory uses STRBx_B3 pin as an additional address pin, A –1 , while using STRBx_B0 and STRBx_B1 as strobe byte-enable pins as shown in Figure 10–14 .
16-Bit-Wide Memory Interface 10-27 TMS320C32 Enhanced External Memory Interface T able 10–10. St r obe-Byte Enable Behavior for 16-Bit-Wide Memory with 8-Bit Data-T ype Size Internal A 0 Active Strobe Byte Enable 0 STRBx_B0 1 STRBx_B1 Figure 10–15.
16-Bit-Wide Memory Interface 10-28 T able 10–1 1. Example of 8-Bit Data-T ype Size and 16-Bit-Wide External Memory Internal Address Bus External Address Pins STRB0_B3 /A –1 Active Strobe Byte Enab.
16-Bit-Wide Memory Interface 10-29 TMS320C32 Enhanced External Memory Interface Figure 10–16. Functional Diagram for 16-Bit Data-T ype Size and 16-Bit External-Memory Width A 23 A 22 A 21 A 20 . . . A 2 A 1 A 0 CS I/O(7-0) A 23 A 22 A 21 A 20 . . . A 2 A 1 A 0 CS I/O(7-0) ’C32 .
16-Bit-Wide Memory Interface 10-30 Case 6: 16-Bit-Wide Memory with 32-Bit Data-T ype Size When the data type size is 32 bits, the ’C32 does not shift the internal address before presenting it to the external address pins. In this case, the memory interface copies the value of the internal address bus to the respective external address pins.
16-Bit-Wide Memory Interface 10-31 TMS320C32 Enhanced External Memory Interface T able 10–13. Example of 16-Bit-Wide Memory With 32-Bit Data-T ype Size Internal Address Bus External Address Pins STR.
8-Bit-Wide Memory Interface 10-32 10.8 8-Bit-Wide Memory Interface ’C32 memory interface to an 8-bit wide external memory uses STRBx_B3 and STRBx_B2 pins as additional address pins, A –1 and A –2 , respectively , while using STRBx_B0 as strobe byte-enable pin as shown in Figure 10–18.
8-Bit-Wide Memory Interface 10-33 TMS320C32 Enhanced External Memory Interface Figure 10–19. Functional Diagram for 8-Bit Data-T ype Size and 8-Bit External-Memory Width A23 A22 A21 A20 . . . A2 CS I/O(7-0) ’C32 A 23 A 22 A 21 A 20 A 19 A 18 . . .
8-Bit-Wide Memory Interface 10-34 Case 8: 8-Bit Wide Memory With 16-Bit Data-T ype Size When the data-type size is 16 bits, the ‘C32 shifts the internal address one bit to the right before presenting it to the external-address pins.
8-Bit-Wide Memory Interface 10-35 TMS320C32 Enhanced External Memory Interface For example, reading or writing to memory locations A04000h to A04002h involves the pins listed in T able 10–15.
8-Bit-Wide Memory Interface 10-36 Figure 10–21. Functional Diagram for 32-Bit Data-T ype Size and 8-Bit External-Memory Width A 24 A 23 A 22 . A 4 A 2 A 1 A 0 CS I / O(7 – 0) ’C32 A 23 A 22 A 21.
8-Bit-Wide Memory Interface 10-37 TMS320C32 Enhanced External Memory Interface For example, reading or writing to memory locations A04000h to A04001h involves the pins listed in T able 10–16.
External Ready Timing Improvement 10-38 10.9 External Ready Timing Improvement The ready (RDY ) timing should relate to the H1 low signal as shown in Figure 10–22 . This is equivalent to the ’C4x ready timing, which increases the time between valid address and the sampling of RDY .
Bus Timing 10-39 TMS320C32 Enhanced External Memory Interface 10.10 Bus Timing This section discusses functional timing of operations on the external memory bus. Detailed timing specifications are contained in the TMS320C32 Data Sheet . The timing of STRB0 and STRB1 bus cycles is identical and discussed in subsection 10.
Bus Timing 10-40 Figure 10–23. Read-Read-Write Sequence for STRBx Active RDY D A R/W STRBx H1 H3 Read Read Write Figure 10–24 shows a zero wait-state write-write-read sequence for STRBx active.
Bus Timing 10-41 TMS320C32 Enhanced External Memory Interface Figure 10–25 shows a one wait-state read sequence and Figure 10–26 shows the write sequence for STRB x active. On the first H1 cycle, RDY is high; therefore, the read or write sequence is extended for one extra cycle.
Bus Timing 10-42 Figure 10–26. One Wait-State Write Sequence for STRBx Active RDY D A R/W STRBx H1 H3 Extra cycle Write 10.10.2 IOSTRB Bus Cycles In contrast to STRB0 and STRB1 bus cycles, IOSTRB full speed (zero wait- state) reads and writes consume two H1 cycles.
Bus Timing 10-43 TMS320C32 Enhanced External Memory Interface Figure 10–27 illustrates a zero wait-state read and write sequence for IOSTRB active. During writes, the data is valid when IOSTRB changes.
Bus Timing 10-44 Figure 10–28. One Wait-State Read Sequence for IOSTRB Active IOSTRB RDY D A R/W H1 H3 Extra cycle Read Figure 10–29. One Wait-State Write Sequence for IOSTRB Active IOSTRB RDY D A.
Bus Timing 10-45 TMS320C32 Enhanced External Memory Interface Figure 10–30. STRBx Read and IOSTRB Write I/O Write Read STRB0,1 IOSTRB RDY D A R/W H1 H3 Figure 10–31.
Bus Timing 10-46 Figure 10–32 and Figure 10–33 illustrate the transitions between STRBx writes and IOSTRB writes and reads, respectively . In these transitions, the address changes on the falling edge of the H3 cycle. Figure 10–32. STRBx Write and IOSTRB Write Write I/O write STRBx IOSTRB RDY D A R/W H1 H3 Figure 10–33.
Bus Timing 10-47 TMS320C32 Enhanced External Memory Interface Figure 10–34 through Figure 10–37 show the transitions between IOSTRB writes/reads and STRBx writes/reads. In these transitions, the address changes on the rising edge of the H3 cycle. Figure 10–34.
Bus Timing 10-48 Figure 10–35. IOSTRB Write and STRBx Read I/O Write Read STRBx IOSTRB RDY D A R/W H1 H3 Figure 10–36. IOSTRB Read and STRBx Write I/O read Write STRBx IOSTRB RDY D A R/W H1 H3.
Bus Timing 10-49 TMS320C32 Enhanced External Memory Interface Figure 10–37. IOSTRB Read and STRBx Read Read I/O Read STRBx IOSTRB RDY D A R/W H1 H3 Figure 10–38 through Figure 10–40 illustrate the transitions between reads and writes.
Bus Timing 10-50 Figure 10–38. IOSTRB Write and Read I/O write IOSTRB RDY D A R/W H1 H3 I/O read Figure 10–39. IOSTRB Write and Write I/O write I/O write IOSTRB RDY D A R/W H1 H3.
Bus Timing 10-51 TMS320C32 Enhanced External Memory Interface Figure 10–40. IOSTRB Read and Read I/O Read I/O Read IOSTRB RDY D A R/W H1 H3 10.10.3 Inactive Bus States Figure 10–41 and Figure 10–42 show the signal states when a bus becomes inactive after an IOSTRB or STRBx , respectively .
Bus Timing 10-52 Figure 10–42. Inactive Bus States Following STRBx Bus Cycle I/O write STRBx RDY D A R/W H1 H3 Bus inactive RDY ignored.
1 1-1 Using the TMS320C31 and TMS320C32 Boot Loaders The ’C31 and ’C32 have on-chip boot loaders that can load and execute pro- grams received from a host processor , standard memory devices (including EPROM), or via serial port. T opic Page 1 1.1 TMS320C31 Boot Loader 1 1-2 .
TMS320C31 Boot Loader 1 1-2 1 1.1 TMS320C31 Boot Loader This section describes how to use the ’C31 microcomputer/boot loader (MCBL/ MP ) function. This feature is unique to the ’C31 and ’C32, and is not available on the ’C30 devices.
TMS320C31 Boot Loader 1 1-3 Using the TMS320C31 and TMS320C32 Boot Loaders T able 1 1–1. Boot-Loader Mode Selection INT0 INT1 INT2 INT3 Loader Mode Memory Addresses 0 1 1 1 External memory Boot 1 ad.
TMS320C31 Boot Loader 1 1-4 1 1.1.3 TMS320C31 Boot-Loading Sequence The following is the sequence of events that occur during the boot load of a source program.
TMS320C31 Boot Loader 1 1-5 Using the TMS320C31 and TMS320C32 Boot Loaders Figure 1 1–2. Boot-Loader Memory-Load Flowchart block loaded address of first Branch to destination Load next block size Bl.
TMS320C31 Boot Loader 1 1-6 Figure 1 1–3. Boot-Loader Serial-Port Load-Mode Flowchart Begin program execution Block size –1 T ransfer data from serial port to destination address port input W ait .
TMS320C31 Boot Loader 1 1-7 Using the TMS320C31 and TMS320C32 Boot Loaders 1 1.1.4 TMS320C31 Boot Data Stream Structure T able 1 1–2 shows the data stream structure. The data stream is composed of a header of 1 (serial-port load) or 2 (memory load) words and one or more blocks of source data.
TMS320C31 Boot Loader 1 1-8 T able 1 1–2. Source Data Stream Structure Wor d † Content V alid Data Entries 1 Memory width (8, 16, or 32 bits) where source program resides 8h, 10h, or 20h, respectively 2 V alue to set the STRB control register See subsection 10.
TMS320C31 Boot Loader 1 1-9 Using the TMS320C31 and TMS320C32 Boot Loaders 1 1.1.4.1 Examples of External TMS320C31 Memory Loads T able 1 1–3 , T able 1 1–4, and T able 1 1–5 show memory images for byte-wide, 16-bit-wide, and 32-bit-wide configured memory (see Figure 4–2 on page 4-6 ).
TMS320C31 Boot Loader 1 1-10 T able 1 1–4. 16-Bit-Wide Configured Memory Address V alue Comments 0x1000 0x10 Memory width = 16 0x1001 0x0000 0x1002 0x1058 Memory type = SWW = 1 1, WCNT = 2 0x1003 0x.
TMS320C31 Boot Loader 1 1-1 1 Using the TMS320C31 and TMS320C32 Boot Loaders 1 1.1.4.2 Serial-Port Loading Boot loads, by way of the ’C31 serial port, are selected by driving the INT3 pin active (low) following reset. The loader automatically configures the serial port for 32-bit fixed-burst-mode reads.
TMS320C31 Boot Loader 1 1-12 T able 1 1–6. TMS320C31 Interrupt and T rap Memory Maps Address Description 809FC1 INT0 809FC2 INT1 809FC3 INT2 809FC4 INT3 809FC5 XINT0 809FC6 RINT0 809FC7 XINT1 (Reser.
TMS320C31 Boot Loader 1 1-13 Using the TMS320C31 and TMS320C32 Boot Loaders 1 1.1.6 TMS320C31 Boot-Loader Precautions The boot loader builds a one-word-deep stack, starting at location 809801h. A void loading code at location 809801h. The interrupt flags are not reset by the boot-loader function.
TMS320C32 Boot Loader 1 1-14 1 1.2 TMS320C32 Boot Loader This section describes how to use the ’C32 microcomputer/boot loader (MCBL/MP ) functions. 1 1.2.1 TMS320C32 Boot-Loader Description The ’C32 boot loader is an enhanced version of that found in the ’C31.
TMS320C32 Boot Loader 1 1-15 Using the TMS320C31 and TMS320C32 Boot Loaders T able 1 1–7. Boot-Loader Mode Selection INT0 INT1 INT2 INT3 Boot Loader Mode Source Program Location 0 1 1 1 External mem.
TMS320C32 Boot Loader 1 1-16 4) Otherwise, the boot loader attempts a memory boot load. Figure 1 1–6 shows the boot-loader memory flow . If the IF register ’s INT0 bit field is set, the source program is loaded from memory location 1000h. If the IF regis- ter ’s INT1 bit field is set, the source program is loaded from memory location 810000h.
TMS320C32 Boot Loader 1 1-17 Using the TMS320C31 and TMS320C32 Boot Loaders Figure 1 1–4. TMS320C32 Boot-Loader Mode-Selection Flowchart No Ye s No Ye s MCBL/MP = 1 Reset Begin Serial-port load No Y.
TMS320C32 Boot Loader 1 1-18 Figure 1 1–5. Boot-Loader Serial-Port Load Flowchart According to the destination address, set corresponding STRB control register data- type size field T ransfer one wo.
TMS320C32 Boot Loader 1 1-19 Using the TMS320C31 and TMS320C32 Boot Loaders Figure 1 1–6. Boot-Loader Memory-Load Flowchart End of source program code (block size = 0)? End of source program code (b.
TMS320C32 Boot Loader 1 1-20 Figure 1 1–7. Handshake Data-T ransfer Operation V alid data V alid data i ii iii iv XF1 XF0 D31-0 IACK 1 1.2.4 TMS320C32 Boot Data Stream Structure T able 1 1–8 shows the data stream structure.
TMS320C32 Boot Loader 1 1-21 Using the TMS320C31 and TMS320C32 Boot Loaders T able 1 1–8. Source Data Stream Structure Wor d † Content V alid Data Entries 1 Memory width (8, 16, or 32 bits) where source program resides 8h, 10h, or 20h, respectively 2 V alue to set the IOSTRB control register at end of boot loader process See Section 10.
TMS320C32 Boot Loader 1 1-22 T able 1 1–8. Source Data Stream Structure (Continued) V alid Data Entries Content Wor d † m + 2 Last block destination memory width and data-type size in the format given in the V alid Data Entries column. SSSSSS6x h ‡ m + 3 First word of last block.
TMS320C32 Boot Loader 1 1-23 Using the TMS320C31 and TMS320C32 Boot Loaders 1 1.2.5 Boot-Loader Hardware Interface The hardware interface for the memory boot load uses the STRBX_B 3 through STRBX_B 0 pins as strobe byte-enable pins (see Figure 1 1–8).
TMS320C32 Boot Loader 1 1-24 The ’C32 boot loader uses the following peripheral memory-mapped registers as a temporary stack: T imer0 counter register (808024h) T imer0 period register (808028h) DMA.
12-1 Peripherals The ’C3x features two timers, a serial port (two serial ports for the ’C30), a nd an on-chip direct memory access (DMA) controller (2-channel DMA controller on the ’C32). These peripheral modules are controlled through memory- mapped registers located on the dedicated peripheral bus.
Timers 12-2 12.1 Timers The ’C3x has two 32-bit general-purpose timer modules. Each timer has two signaling modes and internal or external clocking. Y ou can use the timer modules to signal to the ’C3x or the external world at specified intervals or to count external events.
Timers 12-3 Peripherals 12.1.1 Timer Pins Each timer has one pin associated with the timer clock signal (TCLK) pin. This pin (TCK) is used as a general-purpose I/0 signal, as a timer output, or as an input for an external clock for a timer . Each timer has a TCLK pin: TCLK0 is connected to timer0, TCLK1 to timer1.
Timers 12-4 Figure 12–2. Memory-Mapped Timer Locations T imer0 global control † T imer0 counter ‡ T imer0 period ‡ T imer1 global control † T imer1 counter ‡ T imer1 period ‡ 808020h 808034h 808024h 808028h 808030h 808038h ‡ See Section 12.
Timers 12-5 Peripherals T able 12–1. Timer Global-Control Register Bits Summary Abbreviation Reset V alue Name Description FUNC 0 Function Controls the function of TCLK. If FUNC = 0, TCLK is configured as a general-purpose digital I/O port. If FUNC = 1, TCLK is configured as a timer pin.
Timers 12-6 T able 12–1. Timer Global-Control Register Bits Summary (Continued) Abbreviation Description Name Reset V alue C/P 0 Clock/pulse mode control When C/P = 1, clock mode is chosen, and the signal- ing of the TST A T flag and external output has a 50% duty cycle.
Timers 12-7 Peripherals 12.1.4 Timer-Period and Counter Registers The 32-bit timer-period register is used to specify the frequency of the timer signaling. The timer-counter register is a 32-bit register , which is reset to 0 whenever it increments to the value of the period register .
Timers 12-8 Figure 12–4. Timer Timing 2/f(H1) 1/f(H1) 1/f(CLKSRC) period register/f(CLKSRC) period register/f(CLKSRC) 2 x period register/f(CLKSRC) (a) TST A T and timer output (INV = 0) when C/P = .
Timers 12-9 Peripherals Example 12–1. Timer Output Generation Examples 2H1 2H1 H1 (a) INV = 0, C/P = 0 (pulse mode) timer period = 1 Also, 4H1 H1 (b) INV = 0, C/P = 0 (pulse mode) timer period = 2 6.
Timers 12-10 12.1.6 Timer Operation Modes The timer can receive its input and send its output in several different modes, depending upon the setting of CLKSRC, FUNC, and I /O. The four timer modes of operation are defined in the following sections. 12.
Timers 12-1 1 Peripherals 12.1.6.2 CLKSRC = 1 and FUNC = 1 If CLKSRC = 1 and FUNC = 1 (see Figure 12–6), the timer input comes from the internal clock, and the timer output goes to TCLK. This value can be inverted using INV , and you can read in DA TIN the value output on TCLK.
Timers 12-12 12.1.6.4 CLKSRC = 0 and FUNC = 1 If CLKSRC = 0 and FUNC = 1 (see Figure 12–8), TCLK drives the timer . If INV = 0, all 0-to-1 transitions of TCLK increment the counter . If INV = 1, all 1-to-0 transitions of TCLK increment the counter .
Timers 12-13 Peripherals 12.1.8 Timer Interrupts A timer interrupt is generated whenever the TST A T bit of the timer control register changes from a 0 to a 1. The frequency of timer interrupts depends on whether the timer is set up in pulse mode or clock mode.
Timers 12-14 2) Configure the timer through the timer global-control register (with GO = HLD = 0 ), the timer-counter register , and timer-period register , if necessary . 3) Start the timer by setting the GO/HLD bits of the timer global-control register .
Serial Ports 12-15 Peripherals 12.2 Serial Ports The ’C30 has two totally independent bidirectional serial ports. Both serial ports are identical, and there is a complementary set of control registers in each one. Only one serial port is available on the ’C31 and the ’C32.
Serial Ports 12-16 Figure 12–1 1. Serial Port Block Diagram Receive Section Transmit Section Receive timer (16) Transmit timer (16) Bit counter (8/16/24/32) Bit counter (8/16/24/32) RSR (32) XSR (32.
Serial Ports 12-17 Peripherals Figure 12–12. Memory-Mapped Locations for the Serial Ports Serial-port 0 global control Serial port 0 FSR/DR/CLKR control § Serial port 0 R/X timer control ¶ Serial .
Serial Ports 12-18 Figure 12–13. Serial-Port Global-Control Register 28 RRESET RTINT XINT XTINT 31 30 29 27 26 25 24 23 22 21 20 19 18 17 16 RLEN XLEN FSRP FSXP R/W R/W R/W R/W R/W R/W R/W R/W R/W R.
Serial Ports 12-19 Peripherals T able 12–2. Serial-Port Global-Control Register Bits Summary (Continued) Abbreviation Description Name Reset V alue HS 0 Handshake If HS = 1, the handshake mode is enabled. If HS = 0, the handshake mode is disabled. XCLK SRCE 0 T ransmit clock source If XCLK SRCE = 1, the internal transmit clock is used.
Serial Ports 12-20 T able 12–2. Serial-Port Global-Control Register Bits Summary (Continued) Abbreviation Description Name Reset V alue CLKRP 0 CLKR polarity If CLKRP = 0, CLKR is active (high). If CLKRP = 1, CLKR is active (low). DXP 0 DX polarity If DXP = 0, DX is active (high).
Serial Ports 12-21 Peripherals T able 12–2. Serial-Port Global-Control Register Bits Summary (Continued) Abbreviation Description Name Reset V alue RINT 0 Receive interrupt enable If RINT = 0, the receive interrupt is disabled. If RINT = 1, the receive interrupt is enabled.
Serial Ports 12-22 12.2.2 FSX/DX/CLKX Port-Control Register This 32-bit port-control register controls the function of the serial port FSX, DX, and CLKX pins. The register is shown in Figure 12–14. T able 12–3 shows the register bits, bit names, and bit functions.
Serial Ports 12-23 Peripherals T able 12–3. FSX/DX/CLKX Port-Control Register Bits Summary (Continued) Abbreviation Description Name Reset V alue FSX FUNC 0 FSX function Controls the function of FSX. If FSX FUNC = 0, FSX is configured as a general-purpose digital I/O port.
Serial Ports 12-24 T able 12–4. FSR/DR/CLKR Port-Control Register Bits Summary Abbreviation Reset V alue Name Description CLKR FUNC 0 Clock receive function Controls the function of CLKR. If CLKR FUNC = 0, CLKR is configured as a general-purpose digital I/O port.
Serial Ports 12-25 Peripherals 12.2.4 Receive/T ransmit Timer-Control Register A 32-bit receive/transmit timer-control register contains the control bits for the timer module. At reset, all bits are set to 0. Figure 12–16 shows the register . Bits 5 –0 control the transmitter timer .
Serial Ports 12-26 T able 12–5. Re c ei ve /T r an s mi t Ti me r - Co n tr ol R e gi s te r Re gi st er B it s Su mm ar y ( Co nt i nu ed ) Abbreviation Function Name Reset V alue XCLKSRC 0 T ransmit clock source Specifies the source of the transmit timer clock.
Serial Ports 12-27 Peripherals T able 12–5. Re c ei ve /T r an s mi t Ti me r - Co n tr ol R e gi s te r Re gi st er B it s Su mm ar y ( C on t in ue d) Abbreviation Function Name Reset V alue RCLKSRC 0 Receive timer clock source Specifies the source of the receive timer clock.
Serial Ports 12-28 12.2.6 Receive/T ransmit Timer-Period Register The receive/transmit timer-period register is a 32-bit register (see Figure 12–18 ). Bits 15 –0 are the timer transmit period, and bits 31 –16 are the receive period. Each register specifies the period of the timer and is cleared to 0 at reset .
Serial Ports 12-29 Peripherals Data is shifted to the left (LSB to MSB). Figure 12–20 illustrates what happens when words less than 32 bits are shifted into the serial port. In this figure, it is assumed that an 8-bit word is being received and that the upper three bytes of the receive buffer are originally undefined.
Serial Ports 12-30 Figure 12–21. Serial-Port Clocking in I/O Mode TST A T Timer in XSR T imer in XSR T imer in XSR T imer in XSR TST A T TST A T TST A T DA TIN DA TOUT DA TOUT (NC) DA TIN DA T AOUT .
Serial Ports 12-31 Peripherals Figure 12–22. Serial-Port Clocking in Serial-Port Mode CLKX FUNC = 1 (serial-port mode) CLKX I /O = 1 (output serial-port CLK) XCLK SRC = 0 or 1 (a) TST A T TST A T TS.
Serial Ports 12-32 The transmit ready (XRDY) signal specifies that the data-transmit register (DXR) is available to be loaded with new data. XRDY goes active as soon as the data is loaded into the transmit-shift register (XSR). The last word may still be shifting out when XRDY goes active.
Serial Ports 12-33 Peripherals 12.2.10.1 Continuous Transmit and Receive Modes When you choose continuous mode, consecutive writes do not generate or expect new sync pulse signaling. Only the first word of a block begins with an active synchronization.
Serial Ports 12-34 When the serial port is placed in the handshake mode, the insertion and deletion of a leading 1 for transmitted data, the sending of a 0 for acknowledgement of received data, and the waiting for this acknowledge bit are all performed auto- matically .
Serial Ports 12-35 Peripherals 12.2.12 Serial-Port Functional Operation The following paragraphs and figures illustrate the functional timing of the various serial-port modes of operation.
Serial Ports 12-36 12.2.12.1 Fixed Data-Rate Timing Operation Fixed data-rate serial-port transfers can occur in two varieties: burst mode and continuous mode. In burst mode, transfers of single words are separated by periods of inactivity on the serial port.
Serial Ports 12-37 Peripherals Figure 12–27. Fixed Standard Mode With Back-to-Back Frame Sync A1 AN B1 BN C1 DXR loaded with A XINT DXR loaded with B XINT RINT XINT RINT CLKX/R FSX (Internal) FSR/FS.
Serial Ports 12-38 sync inputs are ignored. Additionally , you should set R/XFSM prior to or during the first word transferred; you must set R/XFSM no later than the transfer of the N –1 bit of the first word, except for transmit operations. For transmit operations in the fixed data-rate mode, XFSM must be set no later than the N –2 bit.
Serial Ports 12-39 Peripherals Figure 12–29. Exiting Fixed Continuous Mode Without Frame Sync, FSX Internal CLKX FSX (internal) DX LOAD DXR SET XFSM RESET XFSM A1 AN B1 BN C1 CN D1 DN E1 EN F1 FN 1st word 2nd word 3rd word 4th word 5th word 12.2.12.
Serial Ports 12-40 V ariable Standard Mode When you transmit continuously in variable data-rate mode with frame sync, timing is the same as for fixed data-rate mode, except for the differences be tw ee n these two modes as described in Section 12.2.12 Serial-Port Functional Operation , on page 12-35.
Serial Ports 12-41 Peripherals Figure 12–32. V ariable Continuous Mode Without Frame Sync CLKX/R FSR/FSX (external) FSX (internal) DX/DR A1 AN B1 BN C1 C2 XINT RINT Load DXR with D read DRR Set R/XFS M DXR loaded with B XINT DXR loaded with A XINT RINT Load DXR with C read DRR R/XV AREN = 1 R/XFSM = 1 12.
Serial Ports 12-42 12.2.14.1 Handshake Mode Example When using the handshake mode, the transmit (FSX/DS/CLKX) and receive (FSR/DR/CLKR) signals transmit and receive data, respectively . Even if the ’C3x serial port is receiving data only with handshake mode, the transmit signals are still needed to transmit the acknowledge signal.
Serial Ports 12-43 Peripherals Example 12–4 and Example 12–5 are serial-port register setups for the above case. (Assume two ’C3xs have the same system clock.
Serial Ports 12-44 Example 12–6. CPU T ransfer With Serial Port T ransmit Polling Method * TITLE: CPU TRANSFER WITH SERIAL-PORT TRANSMIT POLLING METHOD * .GLOBAL START .DATA SOURCE .WORD _ARRAY .BSS _ARRAY,128 ; DATA ARRAY LOCATED IN .BSS SECTION ; THE UNDERSCORE USED IS JUST TO MAKE IT ; ACCESSIBLE FROM C (OPTIONAL) SPORT .
Serial Ports 12-45 Peripherals 12.2.14.3 DMA Transfer With Serial Port Interrupt Example 12–8 and Example 12–9 of Section 12.3.1 1 on page 12-74 use the DMA synchronized to serial port interrupts to transfer data (128 words) from an array buffer to the serial port0 output register .
Serial Ports 12-46 12.2.14.5 Serial Analog-to-Digital (A/D) and Digital-to-Analog (D/A) Interface Example The DSP201/2 and DSP101/2 family of D/As and A/Ds from Burr Brown also offer a zero-glue-logic interface to the ’C3x family of DSPs. The interface is shown in Example 12–7.
Serial Ports 12-47 Peripherals 4) The bit clock drives both the A/D’ s and D/A ’s XCLK input. 5) The ’C3x transmit clock also acts as the input clock on the receive side of the ’C3x serial port. 6) Since the receive clock is synchronous to the internal clock of the ’C3x, the receive clock can run at full speed (that is, f(H1)/2).
DMA Controller 12-48 12.3 DMA Controller The DMA controller is a programmable peripheral that transfers blocks of data to any location in the memory map without interfering with CPU operation. The ’C3x can interface to slow , external memories and peripherals without reducing throughput to the CPU.
DMA Controller 12-49 Peripherals 12.3.1.1 TMS320C30 and TMS320C31 DMA Controller The ’C30 and ’C31 have an on-chip direct memory access (DMA) controller that reduces the need for the CPU to perform input/output functions. The DMA controller can perform input/output operations without interfering with the operation of the CPU.
DMA Controller 12-50 12.3.2 DMA Basic Operation If a block of data is to be transferred from one region in memory to another region in memory (as shown in Figure 12–34), the following sequence is performed: DMA Registers Initialization 1) The source-address register of a DMA channel is loaded with the address of the memory location to read from.
DMA Controller 12-51 Peripherals After the completion of a block transfer , the DMA controller can be programmed to do several things: Stop until reprogrammed (TC = 1) Continue transferring data (TC =.
DMA Controller 12-52 At reset, each DMA-channel control register is set to 0. This makes the DMA channels lower-priority than the CPU, sets up the source address and destination address to be calculated through linear addressing, and configures the DMA channel in the unified mode.
DMA Controller 12-53 Peripherals 12.3.3.1 DMA Global-Control Register The global-control register controls the state in which the DMA controller operates.
DMA Controller 12-54 T able 12–6. DMA Global-Control Register Bits Summary Abbreviation Reset V alue Name Description ST ART 00 DMA start control Controls the state in which the DMA starts and stops.
DMA Controller 12-55 Peripherals T able 12–6. DMA Global-Control Register Bits Summary (Continued) Abbreviation Reset V alue Name Description INCSRC 0 DMA source address increment mode If INCSRC = 1, the source address is incremented after every read.
DMA Controller 12-56 T able 12–6. DMA Global-Control Register Bits Summary (Continued) Abbreviation Reset V alue Name Description DMA0 PRI 00 CPU/DMA channel 0 priority mode (on the DMA0 control register) (’C32 only) DMA1 PRI 00 CPU/DMA channel 1 priority mode (on the DMA1 control register) (‘C32 only) Configures CPU/DMA controller priority .
DMA Controller 12-57 Peripherals 12.3.3.2 Destination-Address and Source-Address Registers The DMA destination-address and source-address registers are 24-bit registers whose contents specify destination and source addresses.
DMA Controller 12-58 12.3.3.3 Transfer-Counter Register The transfer-counter register is a 24-bit register that contains the number of words to be transmitted. Figure 12–40 shows the transfer-counter operation. It is controlled by a 24-bit counter that decrements at the beginning of a DMA memory write.
DMA Controller 12-59 Peripherals Figure 12–40. T ransfer-Counter Operation Halt ? TC=1 Is DMA interrupt generated ? TCINT=1 Is ? to 0 Compare Decrementer T ransfer-counter register Ye s Ye s No No Ye s No 12.3.4 CPU/DMA Interrupt-Enable Register The CPU/DMA interrupt-enable register (IE) is a 32-bit register located in the CPU register file.
DMA Controller 12-60 Figure 12–41. TMS320C30 and TMS320C31 CPU/DMA Interrupt-Enable Register xx EDINT ETINT1 ETINT0 ERINT1 EXINT1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 xx xx xx xx ERINT0 E.
DMA Controller 12-61 Peripherals T able 12–7. CPU/ DMA Interrupt -Enable Regist er Bits Abbreviation Reset V alue Description EINT0 (CPU) 0 CPU external interrupt 0 enable EINT1 (CPU) 0 CPU external.
DMA Controller 12-62 T able 12–7. CPU/DM A Interrupt-Enable R egister Bits (C ontinued) Abbreviation Description Reset V alue ETINT0 (DMA) 0 DMA timer0 interrupt enable (’C30 and ’C31) ETINT1 (D.
DMA Controller 12-63 Peripherals 12.3.5.2 Rotating Priority Scheme In a rotating priority scheme, the last channel serviced becomes the lowest priority channel. The other channel sequentially rotates through the priority list with the lowest channel next to the last-serviced channel becoming the highest priority on the following request.
DMA Controller 12-64 T able 12–8. TMS320C32 DMA PRI Bits and CPU/DMA Arbitration Rules DMA PRI (Bits 13–12) Description 0 0 DMA access is lower priority than the CPU access. If the DMA channel and the CPU request the same resource, then the CPU has priority .
DMA Controller 12-65 Peripherals The DMA and the CPU can respond to the same interrupt if the CPU is not involved in any pipeline conflict or in any instruction that halts instruction fetching. Refer to section 7.6.2 , Interrupt Vector T able and Prioritization , on page 7-29 for more details.
DMA Controller 12-66 Figure 12–44. Mechanism for DMA Source Synchronization Start Disable DMA interrupts globally DMA channel performs a read DMA channel performs a write Go to start Enable DMA inte.
DMA Controller 12-67 Peripherals Source and destination synchronization (SYNC = 1 1) When SYNC = 1 1, the DMA is synchronized to both the source and destination. A read is performed when an interrupt is received. Then, a write is performed on the following interrupt.
DMA Controller 12-68 The data transfer rate for a DMA channel (assuming a single-channel access with no conflicts between CPU or other DMA channels) is as follows: On-chip memory and peripheral DMA re.
DMA Controller 12-69 Peripherals Figure 12–47. DMA Timing When Destination is On Chip Cycles (H1) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 Rate Source on chip R 1 R 2 R 3 R 4 R 5 R 6 R 7 R 8 ( 1.
DMA Controller 12-70 Figure 12–48. DMA Timing When Destination is an STRB, STRB0, STRB1, MSTRB Bus Cycles (H1) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 Rate Source on chip R 1 R 2 R 3 R 4 R 5 Destination STRB, STRB0, W 1 W 1 W 1 W 1 W 2 W 2 W 2 W 2 W 3 W 3 W 3 W 3 W 4 W 4 W 4 W 4 .
DMA Controller 12-71 Peripherals Figure 12–48. DMA Timing When Destination is an STRB, STRB0, STRB1, MSTRB Bus (Continued) Cycles (H1) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 Rate Source IOSTRB.
DMA Controller 12-72 Figure 12–49. DMA Timing When Destination is an IOSTRB Bus Cycles (H1) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 Rate Source on chip R 1 R 2 R 3 R 4 R 5 Destination IOSTRB W .
DMA Controller 12-73 Peripherals 12.3.9 DMA Initialization/Reconfiguration Y ou can control the DMA through memory-mapped registers located on the dedicated peripheral bus. Following is the general procedure for initializing and/or reconfiguring the DMA: 1) Halt the DMA by clearing the ST ART bits of the DMA global-control register .
DMA Controller 12-74 The transfer counter has a zero value. However , the transfer counter is decremented after the DMA read operation finishes (not after the write operation). Nevertheless, a transfer counter with a 0 value can be used as an indication of a transfer completion.
DMA Controller 12-75 Peripherals Example 12–8. Array Initialization With DMA * TITLE: ARRAY INITIALIZATION WITH DMA * .GLOBAL START .DATA DMA .WORD 808000H ; DMA GLOBAL-CONTROL REG ADDRESS RESET .WORD 0C40H ; DMA GLOBAL-CONTROL REG RESET VALUE CONTROL .
DMA Controller 12-76 Example 12–9. DMA T ransfer With Serial-Port Receive Interrupt * TITLE DMA TRANSFER WITH SERIAL PORT RECEIVE INTERRUPT * .GLOBAL START .DATA DMA .WORD 808000H ; DMA GLOBAL-CONTROL REG ADDRESS CONTROL .WORD 0D43H ; DMA GLOBAL-CONTROL REG INITIALIZATION SOURCE .
DMA Controller 12-77 Peripherals Example 12–10 sets up the DMA to transfer data (128 words) from an array buffer to the serial port 0 output register with serial port transmit interrupt XINT0. The DMA sends an interrupt to the CPU when the data transfer completes.
DMA Controller 12-78 Example 12–10. DMA T ransfer With Serial-Port T ransmit Interrupt (Continued) * DMA INITIALIZATION LDI @DMA,AR0 ; POINT TO DMA GLOBAL CONTROL REGISTER LDI @SPORT,AR1 LDI @RESET,.
DMA Controller 12-79 Peripherals T ransfer a 128-word block of data from on-chip memory to off-chip memory and generate an interrupt on completion. Invert the memory or- der; the highest addressed member of the block is to become the lowest addressed member .
13-1 Assembly Language Instructions The ’C3x assembly language instruction set supports numeric-intensive, signal- processing, and general-purpose applications.
Instruction Set 13-2 13.1 Instruction Set The ’C3x instruction set is well suited to digital signal processing and other numeric-intensive applications. All instructions are a single machine word long, and most instructions require one cycle to execute.
Instruction Set 13-3 Assembly Language Instructions 13.1.2 2-Operand Instructions The ’C3x supports 35 2-operand arithmetic and logical instructions. The two operands are the source and destination. The source operand can be a memory word, a register , or a part of the instruction word.
Instruction Set 13-4 13.1.3 3-Operand Instructions Whereas 2-operand instructions have a single source operand (or shift count ) and a destination operand, 3-operand instructions can have two source operands (or one source operand and a count operand) and a destination operand.
Instruction Set 13-5 Assembly Language Instructions T able 13–4. Program-Control Instructions Instruction Description Instruction Description B cond Branch conditionally (standard) IDLE Idle until i.
Instruction Set 13-6 T able 13–6. Interlocked-Operations Instructions Instruction Description Instruction Description LDFI Load floating-point value, interlocked STFI Store floating-point value, interlocked LDII Load integer , interlocked STII Store integer , interlocked SIGI Signal, interlocked 13.
Instruction Set 13-7 Assembly Language Instructions T able 13–7. Parallel Instructions (Continued) (a) Parallel arithmetic with store instructions (Continued) Mnemonic Description FLOA T || STF Conv.
Instruction Set 13-8 T able 13–7. Parallel Instructions (Continued) (b) Parallel load instructions Mnemonic Description LDF || LDF Load floating-point value LDI || LDI Load integer (c) Parallel mult.
Instruction Set 13-9 Assembly Language Instructions 13.1.8 Illegal Instructions The ’C3x has no illegal instruction-detection mechanism. Fetching an illegal (undefined) opcode can cause the execution of an undefined operation. Proper use of the TI TMS320 floating-point software tools will not generate an illegal opcode.
Instruction Set Summary 13-10 13.2 Instruction Set Summary T able 13–8 lists the ’C3x instruction set in alphabetical order . Each table entry provides the instruction mnemonic, description, and operation.
Instruction Set Summary 13-1 1 Assembly Language Instructions T able 13–8. Instruction Set Summary (Continued) Mnemonic Operation Description B cond Branch conditionally (standard) If cond = true: I.
Instruction Set Summary 13-12 T able 13–8. Instruction Set Summary (Continued) Mnemonic Operation Description DB cond Decrement and branch conditionally (standard) AR n – 1 → AR n If cond = true.
Instruction Set Summary 13-13 Assembly Language Instructions T able 13–8. Instruction Set Summary (Continued) Mnemonic Operation Description LDI cond Load integer conditionally If cond = true, src .
Instruction Set Summary 13-14 T able 13–8. Instruction Set Summary (Continued) Mnemonic Operation Description NOP No operation Modify AR n if specified NORM Normalize floating-point value Normalize .
Instruction Set Summary 13-15 Assembly Language Instructions T able 13–8. Instruction Set Summary (Continued) Mnemonic Operation Description RPTB Repeat block of instructions src → RE 1 → ST (RM.
Instruction Set Summary 13-16 T able 13–8. Instruction Set Summary (Continued) Mnemonic Operation Description SUBI Subtract integers Dreg – src → Dreg SUBI3 Subtract integers (3-operand) src 1 .
Parallel Instruction Set Summary 13-17 Assembly Language Instructions 13.3 Parallel Instruction Set Summary T able 13–9 lists the ’C3x instruction set in alphabetical order . Each table entry shows the instruction mnemonic, description, and operation.
Parallel Instruction Set Summary 13-18 T able 13–9. Parallel Instruction Set Summary (Continued) (a) Parallel arithmetic with store instructions (Continued) Mnemonic Description Operation LDF || STF.
Parallel Instruction Set Summary 13-19 Assembly Language Instructions T able 13–9. Parallel Instruction Set Summary (Continued) (a) Parallel arithmetic with store instructions (Continued) Mnemonic D.
Group Addressing Mode Instruction Encoding 13-20 13.4 Group Addressing Mode Instruction Encoding The six addressing types (covered in Section 6.1, Addressing T ypes , on page 6-2 ) form these four gro.
Group Addressing Mode Instruction Encoding 13-21 Assembly Language Instructions Figure 13–1 shows the encoding for the general addressing modes. The notation mod n indicates the modification field that goes with the AR n field. Refer to T able 13–10 on page 13-22 for further information.
Group Addressing Mode Instruction Encoding 13-22 T able 13–10. Indirect Addressing (a) Indirect addressing with displacement Mod Field Syntax Operation Description 00000 *+AR n ( disp ) addr = AR n .
Group Addressing Mode Instruction Encoding 13-23 Assembly Language Instructions T able 13–10. Indirect Addressing (Continued) (c) Indirect addressing with index register IR1 Mod Field Syntax Operati.
Group Addressing Mode Instruction Encoding 13-24 13.4.2 3-Operand Addressing Modes Instructions that use the 3-operand addressing modes, such as ADDI3, LSH3, CMPF3, or XOR3, usually have this form: sr.
Group Addressing Mode Instruction Encoding 13-25 Assembly Language Instructions The following values of AR n and AR m are valid: AR n ,0 ≤ n ≤ 7 AR m ,0 ≤ m ≤ 7 The notation modm or modn indicates the modification field that goes with the AR m or AR n field, respectively .
Group Addressing Mode Instruction Encoding 13-26 address, bits 15–8 the src 3 address, and bits 7–0 the src 4 address. The notations mod n and mod m indicate which modification field goes with which AR n or AR m (auxiliary register) field, respectively .
Group Addressing Mode Instruction Encoding 13-27 Assembly Language Instructions 13.4.4 Conditional-Branch Addressing Modes Instructions using the conditional-branch addressing modes (B cond , B cond D, CALL cond , DB cond , and DB cond D) can perform a variety of conditional operations.
Condition Codes and Flags 13-28 13.5 Condition Codes and Flags The ’C3x provides 20 condition codes (00000–10100, excluding 0101 1) that you can place in the cond field of any of the conditional instructions, such as RETS cond or LDF cond .
Condition Codes and Flags 13-29 Assembly Language Instructions Figure 13–6. Status Register PRGW status (’C32 only) INT config (’C32 only) Note: xx = reserved bit, read as 0 R = read, W = write .
Condition Codes and Flags 13-30 T able 13–12 lists the condition mnemonic, code, description, and flag for each of the 20 condition codes. T able 13–12.
Condition Codes and Flags 13-31 Assembly Language Instructions T able 13–12. Condition Codes and Flags (Continued) (d) Compare to zero Condition Code Description Flag † Z NZ P N NN 00101 001 10 01.
Individual Instructions 13-32 13.6 Individual Instructions This section contains the individual assembly language instructions for the ’C3x. The instructions are listed in alphabetical order . Information for each instruction includes assembler syntax, operation, operands, encoding, description, cycles, status bits, mode bit, and examples.
Individual Instructions 13-33 Assembly Language Instructions T able 13–13. Instruction Symbols Symbol Meaning src src 1 src 2 src 3 src 4 Source operand Source operand 1 Source operand 2 Source oper.
Individual Instructions 13-34 13.6.2 Optional Assembler Syntax Th e a s s e m b le r a l l o w s a r e l a x e d s y n ta x f o r m f o r s o m e i n s t r u c t i o n s . T he s e optional forms simplify the assembly language so that special-case syntax can be ignored.
Individual Instructions 13-35 Assembly Language Instructions Empty expressions are not allowed for the displacement in indirect mode: LDI *+AR0(),R0 is not legal.
Individual Instructions 13-36 Use the syntax in T able 13–14 to designate CPU registers in operands. Note the alternate notation R n , 0 n 27, which is used to designate any CPU register .
Individual Instructions 13-37 Assembly Language Instructions 13.6.3 Individual Instruction Descriptions Each assembly language instruction for the ’C3x is described in this section in alphabetical order . The description includes the assembler syntax, operation, operands, encoding, description, cycles, status bits, mode bit, and examples.
EXAMPLE Example Instruction 13-38 Syntax INST src , dst or INST1 src2 , dst1 || INST2 src3 , dst2 Each instruction begins with an assembler syntax expression. Y ou can place labels either before the command (instruction mnemonic) on the same line or on the preceding line in the first column.
Example Instruction EXAMPLE 13-39 Assembly Language Instructions Opcode INST1 INST2 31 24 23 16 8 7 0 15 00 0 src dst G 31 24 23 16 8 7 0 15 11 dst 1 src 2 dst 2 src 3 00 0 or INST Encoding examples are shown using general addressing and parallel addressing.
EXAMPLE Example Instruction 13-40 Example INST @98AEh,R5 Before Instruction After Instruction R5 07 6690 0000 R5 00 6690 1000 R5 decimal 2.30562500e+02 R5 decimal 1.
Absolute Value of Floating Point ABSF 13-41 Assembly Language Instructions Syntax ABSF src , dst Operation | src | → dst Operands src general addressing modes (G): 0 0 register (R n , 0 ≤ n ≤ 7).
ABSF||STF Parallel ABSF and STF 13-42 Syntax ABSF src2 , dst1 || STF src3 , dst2 Operation | src2 | → dst1 || src3 → dst2 Operands src2 indirect ( disp = 0, 1, IR0, IR1) dst1 register (R n 1, 0 .
Parallel ABSF and STF ABSF||STF 13-43 Assembly Language Instructions Mode Bit OVM Operation is not affected by OVM bit value. Example ABSF *++AR3(IR1) ,R4 STF R4,*– AR7(1) Before Instruction .
ABSI Absolute V alue of Integer 13-44 Syntax ABSI src , dst Operation | src | → dst Operands src general addressing modes (G): 0 0 any CPU register 0 1 direct 1 0 indirect (disp = 0–255, IR0, IR1).
Absolute V alue of Integer ABSI 13-45 Assembly Language Instructions Example 1 ABSI R0,R0 or ABSI R0 Before Instruction After Instruction R0 00 FFFF FFCB R 0 00 0000 0035 –53 53 Example 2 ABSI *AR1,.
ABSI||STI Parallel ABSI and STI 13-46 Syntax ABSI src2 , dst1 || STI src3, dst2 Operation | src2 | → dst1 || src3 → dst2 Operands src2 indirect ( disp = 0, 1, IR0, IR1) dst1 register (R n 1, 0 ≤.
Parallel ABSI and STI ABSI||STI 13-47 Assembly Language Instructions Status Bits These condition flags are modified only if the destination register is R7 – R0.
ADDC Add Integer With Carry 13-48 Syntax ADDC src , dst Operation dst + src + C → dst Operands src general addressing modes (G): 0 0 any CPU register 0 1 direct 1 0 indirect (disp = 0–255, IR0, IR.
Add Integer With Carry , 3-Operand ADDC3 13-49 Assembly Language Instructions Syntax ADDC3 src2 , src1 , dst Operation src1 + src2 + C → dst Operands src1 3-operand addressing modes (T): 0 0 any CPU.
ADDC3 Add Integer With Carry , 3-Operand 13-50 Example 1 ADDC3 *AR5++(IR0),R5,R2 or ADDC3 R5,*AR5++(IR0),R2 Before Instruction After Instruction R2 00 0000 0000 R2 00 0000 0032 R5 00 0000 0066 R5 00 0.
Add Floating-Point V alues ADDF 13-51 Assembly Language Instructions Syntax ADDF src , dst Operation dst + src → dst Operands src general addressing modes (G): 0 0 register (R n , 0 ≤ n ≤ 7) 0 1.
ADDF Add Floating-Point V alues 13-52 Example ADDF *AR4++(IR1),R5 Before Instruction After Instruction R5 05 7980 0000 R5 09 052C 0000 AR 4 809800 AR4 80992B IR 1 12B IR1 12B LUF 0 LUF 0 LV 0 LV 0 UF 0 UF 0 N 0 N 0 Z 0 Z 0 V 0 V 0 C 0 C 0 Data memory 86B2800 86B2800 5.
Add Floating Point, 3-Operand ADDF3 13-53 Assembly Language Instructions Syntax ADDF3 src2 , src1 , dst Operation src1 + src2 → dst Operands src1 3-operand addressing modes (T): 0 0 register (R n 1,.
ADDF3 Add Floating Point, 3-Operand 13-54 Example 1 ADDF3 R6,R5,R1 or ADDF3 R5,R6,R1 Before Instruction After Instruction R1 00 0000 0000 R1 09 052C 0000 R5 05 7980 0000 R5 05 7980 0000 R6 08 6B28 0000 R6 08 6B28 0000 LUF 0 LUF 0 LV 0 LV 0 UF 0 UF 0 N 0 N 0 Z 0 Z 0 V 0 V 0 C 0 C 0 6.
Parallel ADDF3 and STF ADDF3||STF 13-55 Assembly Language Instructions Syntax ADDF3 src2, src1, dst1 || STF src3, dst2 Operation src1 + src2 → dst1 || src3 → dst2 Operands src1 register (R n 1, 0 .
ADDF3||STF Parallel ADDF3 and STF 13-56 OVM Operation is not affected by OVM bit value. Example ADDF3 *+AR3(IR1),R2,R5 || STF R4,*AR2 Before Instruction After Instruction R2 07 0C80 0000 R2 07 0C80 00.
Add Integer ADDI 13-57 Assembly Language Instructions Syntax ADDI src, dst Operation dst + src → dst Operands src general addressing modes (G): 0 0 any CPU register 0 1 direct 1 0 indirect (disp = 0.
ADDI3 Add Integer , 3-Operand 13-58 Syntax ADDI3 <src2 >,<src1 >,<dst > Operation s rc 1 + src2 → dst Operands src1 3-operand addressing modes (T): 0 0 any CPU register 0 1 indirec.
Add Integer , 3-Operand ADDl3 13-59 Assembly Language Instructions Example 1 ADDI3 R4,R7,R5 Before Instruction After Instruction R4 00 0000 00DC R4 00 0000 00DC R5 00 0000 0010 R5 00 0000 017C R7 00 0.
ADDI3||STI Parallel ADDI3 and STI 13-60 Syntax ADDI3 src2, src1, dst1 || STI src3, dst2 Operation src1 + src2 → dst1 || src3 → dst2 Operands src1 register (R n 1, 0 ≤ n 1 ≤ 7) src2 indirect ( .
Parallel ADDl3 and STI ADDl3||STI 13-61 Assembly Language Instructions OVM Operation is affected by OVM bit value. Example ADDI3 *AR0 –– (IR0),R5,R0 STI R3,*AR7 Before Instruction After Ins.
AND Bitwise-Logical AND 13-62 Syntax AND src, dst Operands dst AND src → dst Operands src general addressing modes (G): 0 0 any CPU register 0 1 direct 1 0 indirect (disp = 0–255, IR0, IR1) 1 1 im.
Bitwise-Logical AND, 3-Operand AND3 13-63 Assembly Language Instructions Syntax AND3 src2, src1, dst Operation src1 AND src2 → dst Operands src1 3-operand addressing modes (T): 0 0 any CPU register .
AND3 Bitwise-Logical AND, 3-Operand 13-64 Example 1 AND3 *AR0 –– (IR0),*+AR1,R4 Before Instruction After Instruction R4 00 0000 0000 R4 00 0000 0020 AR0 80 98F4 AR0 80 98A4 AR1 80 9951 AR1 80 9951.
Parallel AND3 and STI AND3||STI 13-65 Assembly Language Instructions Syntax AND3 src2, src1, dst1 STI src3, dst2 Operation src1 AND src2 → dst1 || src3 → dst2 Operands src1 register (R n 1,.
AND3||STI Parallel AND3 and STI 13-66 OVM Operation is not affected by OVM bit value. Example AND3 *+AR1(IR0),R4,R7 || STI R3,*AR2 Before Instruction After Instruction R0 00 0000 0008 R0 00 0000 0008 .
Bitwise-Logical AND With Complement ANDN 13-67 Assembly Language Instructions Syntax ANDN src , dst Operation dst AND ∼ src → dst Operands src general addressing modes (G): 0 0 any CPU register 0 .
ANDN Bitwise-Logical AND With Complement 13-68 Example ANDN @980Ch,R2 Before Instruction After Instruction R2 00 0000 0C2F R2 00 0000 042D DP 080 DP 080 LUF 0 LUF 0 LV 0 LV 0 UF 0 UF 0 N 0 N 0 Z 0 Z 0.
Bitwise-Logical ANDN, 3-Operand ANDN3 13-69 Assembly Language Instructions Syntax ANDN3 src2, src1, dst Operation src1 AND ∼ src2 → dst Operands src1 3-operand addressing modes (T): 0 0 any CPU re.
ANDN3 Bitwise-Logical ANDN, 3-Operand 13-70 Example 1 ANDN3 R5,R3,R7 Before Instruction After Instruction R3 00 0000 0C2F R3 00 0000 0C2F R5 00 0000 0A02 R5 00 0000 0A02 R7 00 0000 0000 R7 00 0000 042.
Arithmetic Shift ASH 13-71 Assembly Language Instructions Syntax ASH count, dst Operation If ( count ≥ 0): dst << count → dst Else: dst >> | count | → dst Operands count general addr.
ASH Arithmetic Shift 13-72 Status Bits These condition flags are modified only if the destination register is R7 – R0. LUF Unaffected LV 1 if an integer overflow occurs; unchanged otherwise UF 0 N M.
Arithmetic Shift, 3-Operand ASH3 13-73 Assembly Language Instructions Syntax ASH3 count, src, dst Operation If ( count ≥ 0): src << count → dst Else: src >> | count | → dst Operands .
ASH3 Arithmetic Shift, 3-Operand 13-74 Status Bits These condition flags are modified only if the destination register is R7 – R0. LUF Unaffected LV 1 if an integer overflow occurs; unchanged otherw.
Arithmetic Shift, 3-Operand ASH3 13-75 Assembly Language Instructions Example 2 ASH3 R1,R3,R5 Before Instruction After Instruction R1 00 FFFF FFF8 R1 00 FFFF FFF8 R3 00 FFFF CB00 R3 00 FFFF CB00 R5 00 0000 0000 R5 00 FFFF FFCB LUF 0 LUF 0 LV 0 LV 0 UF 0 UF 0 N 0 N 1 Z 0 Z 0 V 0 V 0 C 0 C 0 –8 –8 Note: Cycle Count See Section 8.
ASH3||STI Parallel ASH3 and STI 13-76 Syntax ASH3 count, src2, dst1 || STI src3, dst2 Operation If (coun t ≥ 0): src2 << count → dst1 Else: src2 >> | count | → dst1 || src3 → dst2 .
Parallel ASH3 and STI ASH3||STI 13-77 Assembly Language Instructions Arithmetic right shift: sign of src2 → src2 → C If the count operand is 0, no shift is performed, and the C bit is set to 0. The count and dst operands are assumed to be signed integers.
ASH3||STI Parallel ASH3 and STI 13-78 Example ASH3 R1,*AR6++(IR1),R0 || STI R5,*AR2 Before Instruction After Instruction R0 00 0000 0000 R0 00 FFFF FFAE R1 00 0000 FFE8 R1 00 0000 FFE8 R5 00 0000 0035.
Branch Conditionally (Standard) Bcond 13-79 Assembly Language Instructions Syntax B cond src Operation If cond is true: If src is in register-addressing mode (R n , 0 ≤ n ≤ 27), src → PC. If src is in PC-relative mode (label or address), displacement + PC + 1 → PC.
Bcond Branch Conditionally (Standard) 13-80 Example BZ R0 Before Instruction After Instruction R0 00 0003 FF00 R0 00 0003 FF00 PC 2B00 PC 3 FF00 LUF 0 LUF 0 LV 0 LV 0 UF 0 UF 0 N 0 N 0 Z 1 Z 1 V 0 V 0.
Branch Conditionally (Delayed) BcondD 13-81 Assembly Language Instructions Syntax B cond D src Operation If cond is true: If src is in register-addressing mode (R n , 0 ≤ n ≤ 27), src → PC. If src is in PC-relative mode (label or address), displacement + PC + 3 → PC.
BcondD Branch Conditionally (Delayed) 13-82 Example BNZD 36 (36 = 24h) Before Instruction After Instruction PC 0050 PC 0077 LUF 0 LUF 0 LV 0 LV 0 UF 0 UF 0 N 0 N 0 Z 0 Z 0 V 0 V 0 C 0 C 0 Note: Delaye.
Branch Unconditionally (Standard) BR 13-83 Assembly Language Instructions Syntax BR src Operation src → PC Operands src long-immediate addressing mode Opcode 31 24 23 16 8 7 0 15 01 1 0 0 0 0 0 src .
BRD Branch Unconditionally (Delayed) 13-84 Syntax BRD src Operation src → PC Operands src long-immediate addressing mode Opcode 31 24 23 16 8 7 0 15 01 1 0 0 1 0 0 src Description BRD signifies a delayed branch that allows the three instructions after the delayed branch to be fetched before the PC is modified.
Call Subroutine CALL 13-85 Assembly Language Instructions Syntax CALL src Operation Next PC → *++SP src → PC Operands src long-immediate addressing mode Opcode 31 24 23 16 8 7 0 15 0 1100 0 1 0 src Description A call is performed. The next PC value is pushed onto the system stack.
CALLcond Call Subroutine Conditionally 13-86 Syntax CALL cond src Operation If cond is true: Next PC → *++SP If src is in register addressing mode (R n , 0 ≤ n ≤ 27), src → PC. If src is in PC-relative mode (label or address), displacement + PC + 1 → PC.
Call Subroutine Conditionally CALLcond 13-87 Assembly Language Instructions Example CALLNZ R5 Before Instruction After Instruction R5 00 0000 0789 R5 00 0000 0789 PC 0123 PC 0789 SP 809835 SP 809836 L.
CMPF Compare Floating-Point V alue 13-88 Syntax CMPF src, dst Operation dst – src Operands src general addressing modes (G): 0 0 register (R n , 0 ≤ n ≤ 7) 0 1 direct 1 0 indirect (disp = 0–25.
Compare Floating-Point V alue CMPF 13-89 Assembly Language Instructions Example CMPF *+AR4,R6 Before Instruction After Instruction R6 07 0C80 0000 R6 07 0C80 0000 AR4 80 98F2 AR4 80 98F2 LUF 0 LUF 0 LV 0 LV 0 UF 0 UF 0 N 0 N 0 Z 0 Z 1 V 0 V 0 C 0 C 0 Data memory 8098F3h 070C8000 8098F3h 070C8000 1.
CMPF3 Compare Floating-Point V alue, 3-Operand 13-90 Syntax CMPF3 src2, src1 Operation src1 – src2 Operands src1 3-operand addressing modes (T): 0 0 register (R n 1, 0 ≤ n 1 ≤ 7) 0 1 indirect ( .
Compare Floating-Point V alue, 3-Operand CMPF3 13-91 Assembly Language Instructions Example CMPF3 *AR2,*AR3 –– (1) Before Instruction After Instruction AR2 80 9831 AR2 80 9831 AR3 80 9852 AR4 80 9851 LUF 0 LUF 0 LV 0 LV 0 UF 0 UF 0 N 0 N 1 Z 0 Z 0 V 0 V 0 C 0 C 0 Data memory 809831h 77A7000 809831h 77A7000 809852h 57A2000 809852h 57A2000 2.
CMPI Compare Integer 13-92 Syntax CMPI src, dst Operation dst – src Operands src general addressing modes (G): 0 0 register (R n , 0 ≤ n ≤ 27) 0 1 direct 1 0 indirect (disp = 0–255, IR0, IR1) .
Compare Integer , 3-Operand CMPI3 13-93 Assembly Language Instructions Syntax CMPI3 src2, src1 Operation src1 – src2 Operands src1 3-operand addressing modes (T): 0 0 register (R n 1, 0 ≤ n 1 ≤ .
CMPI3 Compare Integer , 3-Operand 13-94 Example CMPI3 R7,R4 Before Instruction After Instruction R4 00 0000 0898 R4 00 0000 0898 R7 00 0000 03E8 R7 00 0000 03E8 LUF 0 LUF 0 LV 0 LV 0 UF 0 UF 0 N 0 N 0 Z 0 Z 0 V 0 V 0 C 0 C 0 2200 1000 2200 1000 Note: Cycle Count See Section 8.
Decrement and Branch Conditionally (Standard) DBcond 13-95 Assembly Language Instructions Syntax DB cond AR n, src Operation AR n – 1 → AR n If cond is true and AR n ≥ 0 : If src is in register addressing mode (R n , 0 ≤ n ≤ 27), src → PC.
DBcond Decrement and Branch Conditionally (Standard) 13-96 Cycles 4 Status Bits LUF Unaffected LV Unaffected UF Unaffected N Unaffected Z Unaffected V Unaffected C Unaffected OVM Operation is not affected by OVM bit value.
Decrement and Branch Conditionally (Delayed) DBcondD 13-97 Assembly Language Instructions Syntax DB cond D AR n , src Operation AR n – 1 → AR n If cond is true and AR n ≥ 0: If src is in register addressing mode (R n , 0 ≤ n ≤ 27) src → PC If src is in PC-relative mode (label or address) displacement + PC + 3 → PC.
DBcondD Decrement and Branch Conditionally (Delayed) 13-98 Cycles 1 Status Bits LUF Unaffected LV Unaffected UF Unaffected N Unaffected Z Unaffected V Unaffected C Unaffected OVM Operation is not affected by OVM bit value.
Floating-Point-to-Integer Conversion FIX 13-99 Assembly Language Instructions Syntax FIX src, dst Operation fix (src ) → dst Operands src general addressing modes (G): 0 0 register (R n , 0 ≤ n .
FIX Floating-Point-to-Integer Conversion 13-100 Example FIX R1,R2 Before Instruction After Instruction R1 0A 2820 0000 R1 0A 2820 0000 R2 00 0000 0000 R2 00 0000 0541 LUF 0 LUF 0 LV 0 LV 0 UF 0 UF 0 N 0 N 0 Z 0 Z 0 V 0 V 0 C 0 C 0 1.
Parallel FIX and STI FIX||STI 13-101 Assembly Language Instructions Syntax FIX src2, dst1 || STI src3 , dst2 Operation fix( src2 ) → dst1 || src3 → dst2 Operands src2 indirect ( disp = 0, 1, IR0, .
FIX||STI Parallell FIX and STI 13-102 Status Bits These condition flags are modified only if the destination register is R7 – R0. LUF Unaffected LV 1 if an integer overflow occurs; unchanged otherwi.
Integer-to-Floating-Point Conversion FLOA T 13-103 Assembly Language Instructions Syntax FLOA T src, dst Operation float (src) → dst Operands src general addressing modes (G): 0 0 register (R n , 0 .
FLOA T Integer-to-Floating-Point Conversion 13-104 Example FLOAT *++AR2(2),R5 Before Instruction After Instruction R5 00 034C 2000 R5 00 72E0 0000 AR2 80 9800 AR2 80 9802 LUF 0 LUF 0 LV 0 LV 0 UF 0 UF 0 N 0 N 0 Z 0 Z 0 V 0 V 0 C 0 C 0 Data memory 809802 0AE 809802 0AE 174 1.
Parallel FLOA T and STF FLOA T||STF 13-105 Assembly Language Instructions Syntax FLOA T src2, dst1 || STF src3 , dst2 Operation float (src2 ) → dst1 || src3 → dst2 Operands src2 indirect ( disp = .
FLOA T||STF Parallel FLOA T and STF 13-106 Example FLOAT *+AR2(IR0),R6 || STF R7,*AR1 Before Instruction After Instruction R6 00 0000 0000 R6 07 2E00 0000 R7 03 4C20 0000 R7 03 4C20 0000 AR1 80 9933 A.
Interrupt Acknowledge IACK 13-107 Assembly Language Instructions Syntax IACK src Operation Perform a dummy read operation with IACK = 0. At end of dummy read, set IACK to 1.
IACK Interrupt Acknowledge 13-108 Example IACK *AR5 Before Instruction After Instruction IACK 1 IACK 1 PC 300 PC 301 LUF 0 LUF 0 LV 0 LV 0 UF 0 UF 0 N 0 N 0 Z 0 Z 0 V 0 V 0 C 0 C 0.
Idle Until Interrupt IDLE 13-109 Assembly Language Instructions Syntax IDLE Operation 1 → ST(GIE) Next PC → PC Idle until interrupt. Operands None Opcode 31 24 23 16 8 7 0 15 00 0 0 0 0 1 0 1 00 0.
IDLE2 Low-Power Idle 13-1 10 Syntax IDLE2 (supported by: ’LC31, ’C32, ’C30 silicon revision 7.x or greater , ’C31 silicon revision 5.x or greater) Operation 1 → ST(GIE) Next PC → PC Idle until interrupt.
Low-Power Idle IDLE2 13-1 1 1 Assembly Language Instructions For correct device operation, the three instructions after a delayed branch should not be IDLE or IDLE2 instructions. Cycles 1 Status Bits LUF Unaffected LV Unaffected UF Unaffected N Unaffected Z Unaffected V Unaffected C Unaffected OVM Operation is not affected by OVM bit value.
LDE Load Floating-Point Exponent 13-1 12 Syntax LDE src, dst Operation src ( exp ) → dst ( exp ) Operands src general addressing modes (G): 0 0 register (R n , 0 ≤ n ≤ 7) 0 1 direct 1 0 indirect.
Load Floating-Point Exponent LDE 13-1 13 Assembly Language Instructions Example LDE R0,R5 Before Instruction After Instruction R0 02 0005 6F30 R0 02 0005 6F30 R5 0A 056F E332 R5 02 056F E332 LUF 0 LUF 0 LV 0 LV 0 UF 0 UF 0 N 0 N 0 Z 0 Z 0 V 0 V 0 C 0 C 0 4.
LDF Load Floating-Point V alue 13-1 14 Syntax LDF src, dst Operation src → dst Operands src general addressing modes (G): 0 0 register (R n , 0 ≤ n ≤ 7) 0 1 direct 1 0 indirect (disp = 0–255, .
Load Floating-Point V alue Conditionally LDFcond 13-1 15 Assembly Language Instructions Syntax LDF cond src, dst Operation If cond is true: src → dst.
LDFcond Load Floating-Point V alue Conditionally 13-1 16 Example LDFZ R3,R5 Before Instruction After Instruction R3 2C FF2C D500 R3 2C FF2C D500 R5 5F 0000 003E R5 2C FF2C D500 LUF 0 LUF 0 LV 0 LV 0 UF 0 UF 0 N 0 N 0 Z 1 Z 1 V 0 V 0 C 0 C 0 1.77055560e+13 3.
Load Floating-Point V alue, Interlocked LDFI 13-1 17 Assembly Language Instructions Syntax LDFI src, dst Operation Signal interlocked operation src → dst Operands src general addressing modes (G): 0.
LDFI Load Floating-Point V alue, Interlocked 13-1 18 Example LDFI *+AR2,R7 Before Instruction After Instruction R7 00 0000 0000 R7 05 84C0 0000 AR2 80 98F1 AR2 80 98F1 LUF 0 LUF 0 LV 0 LV 0 UF 0 UF 0 N 0 N 0 Z 0 Z 0 V 0 V 0 C 0 C 0 Data memory 8098F2h 584C000 8098F2h 584C000 –6.
Parallel LDF and LDF LDF||LDF 13-1 19 Assembly Language Instructions Syntax LDF src2, dst2 || LDF src1, dst1 Operation src2 → dst2 || src1 → dst1 Operands src1 indirect ( disp = 0, 1, IR0, IR1) ds.
LDF||LDF Parallel LDF and LDF 13-120 Example LDF * –– AR1(IR0),R7 || LDF *AR7++(1),R3 Before Instruction After Instruction R3 00 0000 0000 R0 00 0000 0008 R7 00 0000 0000 R3 05 7B40 0000 AR1 80 98.
Parallel LDF and STF LDF||STF 13-121 Assembly Language Instructions Syntax LDF src2, dst1 || STF src3, dst2 Operation src2 → dst1 || src3 → dst2 Operands src2 indirect ( disp = 0, 1, IR0, IR1) dst.
LDF||STF Parallel LDF and STF 13-122 Example LDF *AR2 –– (1),R1 || STF R3,*AR4++(IR1) Before Instruction After Instruction R1 00 0000 0000 R1 07 0C80 0000 R3 05 7B40 0000 R3 05 7B40 0000 AR2 80 98.
Load Integer LDI 13-123 Assembly Language Instructions Syntax LDI src, dst Operation src → dst Operands src general addressing modes (G): 0 0 any CPU register 0 1 direct 1 0 indirect (disp = 0–255.
LDI Load Integer 13-124 Example LDI *–AR1(IR0),R5 Before Instruction After Instruction R5 00 0000 03C5 R5 00 0000 0026 AR1 2C AR1 2C IR0 5 IR0 5 LUF 0 LUF 0 LV 0 LV 0 UF 0 UF 0 N 0 N 0 Z 0 Z 0 V 0 V.
Load Integer Conditionally LDIcond 13-125 Assembly Language Instructions Syntax LDI cond src, dst Operation If cond is true: src → dst, Else: dst is unchanged.
LDIcond Load Integer Conditionally 13-126 Example LDIZ *ARO++,R6 Before Instruction After Instruction R6 00 0000 0FE2 R6 00 0000 0FE2 AR0 80 98F0 AR0 80 98F1 LUF 0 LUF 0 LV 0 LV 0 UF 0 UF 0 N 0 N 0 Z .
Load Integer , Interlocked LDII 13-127 Assembly Language Instructions Syntax LDII src, dst Operation Signal interlocked operation src → dst Operands src general addressing modes (G): 0 1 direct 1 0 .
LDII Load Integer , Interlocked 13-128 Example LDII @985Fh,R3 Before Instruction After Instruction R3 00 0000 0000 R3 00 0000 00DC DP 80 DP 80 LUF 0 LUF 0 LV 0 LV 0 UF 0 UF 0 N 0 N 0 Z 0 Z 0 V 0 V 0 C.
Parallel LDI and LDI LDI||LDI 13-129 Assembly Language Instructions Syntax LDI src 2 , dst2 || LDI src1, dst1 Operation src2 → dst2 || src1 → dst1 Operands src1 indirect ( disp = 0, 1, IR0, IR1) d.
LDI||LDI Parallel LDI and LDI 13-130 Example LDI *–AR1(1),R7 || LDI *AR7++(IR0),R1 Before Instruction After Instruction R1 00 0000 0000 R1 00 0000 02EE R7 00 0000 0000 R7 00 0000 00FA AR1 80 9826 AR.
Parallel LDI and STI LDI||STI 13-131 Assembly Language Instructions Syntax LDI src2, dst1 || STI src3, dst2 Operation src2 → dst1 || src3 → dst2 Operands src2 indirect ( disp = 0, 1, IR0, IR1) dst.
LDI||STI Parallel LDI and STI 13-132 Example LDI *–AR1(1),R2 || STI R7,*AR5++(IR0) Before Instruction After Instruction R2 00 0000 0000 R2 00 0000 00DC R7 00 0000 0035 R7 00 0000 0035 AR1 80 98E7 AR.
Load Floating-Point Mantissa LDM 13-133 Assembly Language Instructions Syntax LDM src, dst Operation src ( man ) → dst ( man ) Operands src general addressing modes (G): 0 0 register (R n , 0 ≤ n .
LDP Load Data-Page Pointer 13-134 Syntax LDP src, DP Operation src → data-page pointer Operands src is the 8 MSBs of the absolute 24-bit source address ( src ).
Divide Clock by 16 LOPOWER 13-135 Assembly Language Instructions Syntax LOPOWER (supported by: ’LC31 and ’C32, ’C31 silicon revision 5.0 or greater , ’C30 silicon revision 7.
LSH Logical Shift 13-136 Syntax LSH count, dst Operation If count ≥ 0: dst << count → dst Else: dst >> | count | → dst Operands count general addressing modes (G): 0 0 any CPU regist.
Logical Shift LSH 13-137 Assembly Language Instructions Cycles 1 Status Bits These condition flags are modified only if the destination register is R7 – R0.
LSH3 Logical Shift, 3-Operand 13-138 Syntax LSH3 count, src, dst Operation If count ≥ 0: src << count → dst Else: src >> | count | → dst Operands src 3-operand addressing modes (T): .
Logical Shift, 3-Operand LSH3 13-139 Assembly Language Instructions Cycles 1 Status Bits These condition flags are modified only if the destination register is R7 – R0.
LSH3 Logical Shift, 3-Operand 13-140 Example 2 LSH3 *–AR4(IR1),R5,R3 Before Instruction After Instruction R3 00 0000 0000 R3 00 0001 2C00 R5 00 12C0 0000 R5 00 12C0 0000 AR4 80 9908 AR4 80 9908 IR1 .
Parallel LSH3 and STI LSH3||STI 13-141 Assembly Language Instructions Syntax LSH3 c ount, src2, dst1 || STI src3 , dst2 Operation If count ≥ 0: src2 << count → dst1 Else: src2 >> | cou.
LSH3||STI Parallel LSH3 and STI 13-142 Logical right shift: 0 → src2 → C If the count operand is 0, no shift is performed, and the carry bit is set to 0. The count operand is assumed to be a 7-bit signed integer , and the src2 and dst1 operands are assumed to be unsigned integers.
Parallel LSH3 and STI LSH3||STI 13-143 Assembly Language Instructions Example 1 LSH3 R2,*++AR3(1),R0 || STI R4,*–AR5 Before Instruction After Instruction R0 00 0000 0000 R0 00 AC00 0000 R2 00 0000 0.
LSH3||STI Parallel LSH3 and STI 13-144 Example 2 LSH3 R7,*AR2 –– (1),R2 || STI R0,*+AR0(1) Before Instruction After Instruction R0 00 0000 012C R0 00 0000 012C R2 00 0000 0000 R2 00 0002 C000 R7 0.
Restore Clock to Regular Speed MAXSPEED 13-145 Assembly Language Instructions Syntax M A XSPEED (supported by ’C31, ’C32, ’C31 silicon revision 5.
MPYF Multiply Floating-Point V alue 13-146 Syntax MPYF src, dst Operation dst × src → dst Operands src general addressing modes (G): 0 0 register (R n , 0 ≤ n ≤ 7) 0 1 direct 1 0 indirect (disp.
Multiply Floating-Point V alue, 3-Operand MPYF3 13-147 Assembly Language Instructions Syntax MPYF3 src2, src1, dst Operation src1 × src2 → dst Operands src1 3-operand addressing modes (T): 0 0 regi.
MPYF3 Multiply Floating-Point V alue, 3-Operand 13-148 Example 1 MPYF3 R0,R7,R1 Before Instruction After Instruction R0 05 7B40 0000 R0 05 7B40 0000 R1 00 0000 0000 R1 0D 306A 3000 R7 07 33C0 0000 R7 07 33C0 0000 LUF 0 LUF 0 LV 0 LV 0 UF 0 UF 0 N 0 N 0 Z 0 Z 0 V 0 V 0 C 0 C 0 1.
Parallel MPYF3 and ADDF3 MPYF3||ADDF3 13-149 Assembly Language Instructions Syntax MPYF3 srcA, srcB, dst1 || ADDF3 srcC, srcD, dst2 Operation srcA × srcB → dst1 || srcC + srcD → dst2 Operands src.
MPYF3||ADDF3 Parallel MPYF3 and ADDF3 13-150 This instruction’s operands have been augmented in the following devices: ’C31 silicon version 6.0 or greater ’C32 silicon version 2.
Parallel MPYF3 and ADDF3 MPYF3||ADDF3 13-151 Assembly Language Instructions 10 src1 × src2, src3 + src4 11 src3 × src1, src2 + src4 Opcode 31 24 23 16 8 7 0 15 10 0 0 00 src 4 src 3 P src 1 src 2 d1 d2 Description A floating-point multiplication and a floating-point addition are performed in parallel.
MPYF3||ADDF3 Parallel MPYF3 and ADDF3 13-152 Example MPYF3 *AR5++(1),* –– AR1(IR0),R0 || ADDF3 R5,R7,R3 Note: Cycle Count One cycle if: src3 and src4 are in internal memory src3 is in internal mem.
Parallel MPYF3 and STF MPYF3||STF 13-153 Assembly Language Instructions Syntax MPYF3 src2, src1, dst || STF src3, dst2 Operation src1 × src2 → dst1 || src3 → dst2 Operands src1 register (R n 1, 0.
MPYF3||STF Parallel MPYF3 and STF 13-154 Status Bits These condition flags are modified only if the destination register is R7 – R0. LUF 1 if a floating-point underflow occurs; 0 unchanged otherwise.
Parallel MPYF3 and SUBF3 MPYF3||SUBF3 13-155 Assembly Language Instructions Syntax MPYF3 srcA, srcB, dst1 || SUBF3 srcC, srcD, dst2 Operation srcA × srcB → dst1 || srcD – srcC → dst2 Operands s.
MPYF3||ADDF3 Parallel MPYF3 and ADDF3 13-156 This instruction’s operands have been augmented in the following devices: ’C31 silicon version 6.0 or greater ’C32 silicon version 2.
Parallel MPYF3 and SUBF3 MPYF3||SUBF3 13-157 Assembly Language Instructions Opcode 31 24 23 16 8 7 0 15 1 0 00 01 src 4 src 3 P src 1 src 2 d1 d2 Description A floating-point multiplication and a floating-point subtraction are performed in parallel. All registers are read at the beginning and loaded at the end of the execute cycle.
MPYF3||SUBF3 Parallel MPYF3 and SUBF3 13-158 Status Bits These condition flags are modified only if the destination register is R7 – R0. LUF 1 if a floating-point underflow occurs; unchanged otherwi.
Multiply Integer MPYI 13-159 Assembly Language Instructions Syntax MPYI src, dst Operation dst × src → dst Operands src general addressing modes (G): 0 0 any CPU register 0 1 direct 1 0 indirect (d.
MPYI Multiply Integer 13-160 Example MPYI R1,R5 Before Instruction After Instruction R1 00 0033 C251 R1 00 0033 C251 R5 00 0078 B600 R5 00 E21D 9600 LUF 0 LUF 0 LV 0 LV 1 UF 0 UF 0 N 0 N 1 Z 0 Z 0 V 0.
Multiply Integer , 3-Operand MPYI3 13-161 Assembly Language Instructions Syntax MPYI3 src2, src1, dst Operation src1 × src2 → dst Operands src1 3-operand addressing modes (T): 0 0 any CPU register .
MPYI3 Multiply Integer , 3-Operand 13-162 Example 1 MPYI3 *AR4,*–AR1(1),R2 Before Instruction After Instruction R2 00 0000 0000 R2 00 0000 94AC AR1 80 98F3 AR1 80 98F3 AR4 80 9850 AR4 80 9850 LUF 0 .
Parallel MPYI3 and ADDI3 MPYI3||ADDI3 13-163 Assembly Language Instructions Syntax MPYI3 srcA, srcB, dst1 || ADDI3 srcC, srcD, dst2 Operation srcA × srcB → dst1 || srcD + srcC → dst2 Operands src.
MPYI3||ADDI3 Parallel MPYI3 and ADDI3 13-164 This instruction’s operands have been augmented in the following devices: ’C31 silicon version 6.0 or greater ’C32 silicon version 2.
Parallel MPYI3 and ADDI3 MPYI3||ADDI3 13-165 Assembly Language Instructions Opcode 31 24 23 16 8 7 0 15 10 0 01 0 P src 4 src 3 src 1 src 2 d1 d2 Description An integer multiplication and an integer addition are performed in parallel. All registers are read at the beginning and loaded at the end of the execute cycle.
MPYl3||ADDl3 Parallel MPYl3 and ADD13 13-166 Before Instruction After Instruction R0 00 0000 0000 R0 00 0000 07D0 R3 00 0000 0000 R3 00 0000 0000 R4 00 0000 0064 R4 00 0000 0064 R7 00 0000 0014 R7 00 .
Parallel MPYI3 and STI MPYI3||STI 13-167 Assembly Language Instructions Syntax MPYI3 src2, src1, dst1 || STI src3, dst2 Operation src1 × src2 → dst1 || src3 → dst2 Operands src1 register (R n 1, .
MPYI3||STI Parallel MPYl3 and STI 13-168 Status Bits These condition flags are modified only if the destination register is R7 – R0. LUF Unaffected LV 1 if an integer overflow occurs; unchanged othe.
Parallel MPYI3 and SUBI3 MPYI3||SUBI3 13-169 Assembly Language Instructions Syntax MPYI3 srcA, srcB, dst1 || SUBI3 srcC, srcD, dst2 Operation srcA × srcB → dst1 || srcD – srcC → dst2 Operands s.
MPYI3||SUBI3 Parallel MPYI3 and SUBI3 13-170 This instruction’s operands have been augmented in the following devices: ’C31 silicon version 6.0 or greater ’C32 silicon version 2.
Parallel MPYI3 and SUBI3 MPYI3||SUBI3 13-171 Assembly Language Instructions V ersion 5.0 or later P srcA srcB srcD srcC 00 src3 × src4, src1 + src2 01 src3 × src1, src4 + src2 10 src1 × src2, src3 .
MPYI3||SUBI3 Parallel MPYI3 and SUBI3 13-172 or MPYI3 *++AR0(1),R2,R0 || SUBI3 *AR5 –– (IR1),R4,R2 Before Instruction After Instruction R0 00 0000 0000 R0 00 0000 1324 R2 00 0000 0032 R2 00 0000 0.
Negative Integer With Borrow NEGB 13-173 Assembly Language Instructions Syntax NEGB src, dst Operation 0 – src – C → dst Operands src general addressing modes (G): 0 0 any CPU register 0 1 direc.
NEGF Negate Floating-Point V alue 13-174 Syntax NEGF src, dst Operation 0 – src → dst Operands src general addressing modes (G): 0 0 register (R n , 0 ≤ n ≤ 7) 0 1 direct 1 0 indirect (disp = .
Negate Floating-Point V alue NEGF 13-175 Assembly Language Instructions Example NEGF *++AR3(2),R1 Before Instruction After Instruction R1 05 7B40 0025 R1 07 F380 0000 AR3 80 9800 AR3 80 9802 LUF 0 LUF 0 LV 0 LV 0 UF 0 UF 0 N 0 N 0 Z 0 Z 0 V 0 V 0 C 0 C 0 Data memory 809802h 70C8000 809802h 70C8000 6.
NEGF||STF Parallel NEGF and STF 13-176 Syntax NEGF src2, dst1 || STF src3, dst2 Operation 0 – src2 → dst1 || src3 → dst2 Operands src2 indirect ( disp = 0, 1, IR0, IR1) dst1 register (R n 1, 0 .
Parallel NEGF and STF NEGF||STF 13-177 Assembly Language Instructions Example NEGF *AR4 –– (1),R7 || STF R2,*++AR5(1) Before Instruction After Instruction R2 07 33C0 0000 R2 07 33C0 0000 R7 00 000.
NEGI Negate Integer 13-178 Syntax NEGI src, dst Operation 0 – src → dst Operands src general addressing modes (G): 0 0 any CPU register 0 1 direct 1 0 indirect (disp = 0–255, IR0, IR1) 1 1 immed.
Parallel NEGI and STI NEGI||STI 13-179 Assembly Language Instructions Syntax NEGI src2, dst1 || STI src3, dst2 Operation 0 – src2 → dst1 || src3 → dst2 Operands src2 indirect ( disp = 0, 1, IR0,.
NEGI||STI Parallel NEGI and STI 13-180 Example NEGI *–AR3,R2 || STI R2,*AR1++ Before Instruction After Instruction R2 00 0000 0019 R2 00 FFFF FF24 AR1 80 98A5 AR1 80 98A6 AR3 80 982F AR3 80 982F LUF.
No Operation NOP 13-181 Assembly Language Instructions Syntax NOP src Operation No ALU or multiplier operations. AR n is modified if src is specified in indirect mode.
NORM Normalize 13-182 Syntax NORM src, dst Operation norm ( src ) → dst Operands src general addressing modes (G): 0 0 register (R n , 0 ≤ n ≤ 7) 0 1 direct 1 0 indirect (disp = 0–255, IR0, IR.
Normalize NORM 13-183 Assembly Language Instructions Example NORM R1,R2 Before Instruction After Instruction R1 04 0000 3AF5 R1 04 0000 3AF5 R2 07 0C80 0000 R2 F2 6BD4 0000 LUF 0 LUF 0 LV 0 LV 0 UF 0 UF 0 N 0 N 0 Z 0 Z 0 V 0 V 0 C 0 C 0 1.
NOT Bitwise-Logical Complement 13-184 Syntax NOT src, dst Operation ∼ src → dst Operands src general addressing modes (G): 0 0 any CPU register 0 1 direct 1 0 indirect (disp = 0–255, IR0, IR1) 1.
Bitwise-Logical Complement NOT 13-185 Assembly Language Instructions Example NOT @982Ch,R4 Before Instruction After Instruction R4 00 0000 0000 R4 00 FFFF A1D0 DP 080 DP 080 LUF 0 LUF 0 LV 0 LV 0 UF 0.
NOT||STI Parallel NOT and STI 13-186 Syntax NOT src2, dst1 || STI src3, dst2 Operation ∼ src2 → dst1 || src3 → dst2 Operands src2 indirect ( disp = 0, 1, IR0, IR1) dst1 register (R n 1, 0 ≤ n .
Parallel NOT and STI NOT||STI 13-187 Assembly Language Instructions Example NOT *+AR2,R3 || STI R7,* –– AR4 (IR1) Before Instruction After Instruction R3 00 0000 0000 R3 00 FFFF F3D0 R7 00 0000 00.
OR Bitwise-Logical OR 13-188 Syntax OR src, dst Operation dst OR src → dst Operands src general addressing modes (G): 0 0 any CPU register 0 1 direct 1 0 indirect (disp = 0–255, IR0, IR1) 1 1 imme.
Bitwise-Logical OR OR 13-189 Assembly Language Instructions Example OR *++AR1(IR1),R2 Before Instruction After Instruction R2 00 1256 0000 R2 00 1256 2BCD AR1 80 9800 AR1 80 9804 IR1 4 IR1 4 LUF 0 LUF.
OR3 Bitwise-Logical OR, 3-Operand 13-190 Syntax OR3 src2, src1, dst Operation src1 OR src2 → dst Operands src1 3-operand addressing modes (T): 0 0 register (R n 1, 0 ≤ n 1 ≤ 27) 0 1 indirect ( d.
Bitwise-Logical OR, 3-Operand OR3 13-191 Assembly Language Instructions Example OR3 *++AR1(IR1),R2,R7 Before Instruction After Instruction R2 00 1256 0000 R2 00 1256 0000 R7 00 0000 0000 R7 0 1256 2BC.
OR3||STI Parallel OR3 and STI 13-192 Syntax OR3 src2, src1, dst1 || STI src3, dst2 Operation src1 OR src2 → dst1 | src3 → dst2 Operands src1 register (R n 1, 0 ≤ n 1 ≤ 7) src2 indirect ( disp .
Parallel OR3 and STI OR3||STI 13-193 Assembly Language Instructions Status Bits These condition flags are modified only if the destination register is R7 – R0. LUF Unaffected LV Unaffected UF 0 N MSB of the output Z 1 if a 0 result is generated; 0 otherwise V 0 C Unaffected OVM Operation is not affected by OVM bit value.
POP Pop Integer 13-194 Syntax POP dst Operation *SP– – → dst Operands dst register (R n , 0 ≤ n ≤ 27) Opcode 31 24 23 16 8 7 0 15 00 0 01 0 1 0 1 dst 1 0 0 0 0 00 0 0 0 0 0 00 0 00 0 Description The top of the current system stack is popped and loaded into the dst register (32 LSBs).
Pop Floating-Point V alue POPF 13-195 Assembly Language Instructions Syntax POPF dst Operation *SP– – → dst1 Operands dst register (R n , 0 ≤ n ≤ 7) Opcode 31 24 23 16 8 7 0 15 00 0 0 1 0 1 1 1 dst 0 0 1 0 00 000 0 0 00 0 0 0 0 0 0 Description The top of the current system stack (32 MSBs) is popped and loaded into the dst register .
PUSH PUSH Integer 13-196 Syntax PUSH src Operation src → *++SP Operands src register (R n , 0 ≤ n ≤ 27) Opcode 31 24 23 16 8 7 0 15 00 0 0 1 1 1 0 1 src 0 0 1 00 0 0 0 00 0 00 000 00 0 Description The contents of the src register (32 LSBs) are pushed on the current system stack.
PUSH Floating-Point V alue PUSHF 13-197 Assembly Language Instructions Syntax PUSHF src Operation src → *++SP Operands src register (R n , 0 ≤ n ≤ 7) Opcode 31 24 23 16 8 7 0 15 00 0 0 1 1 1 1 1 src 0 0 1 00 0 0 0 0 0 0 00 0 0 0 0 00 Description The contents of the src register (32 MSBs) are pushed on the current system stack.
RETIcond Return From Interrupt Conditionally 13-198 Syntax RETI cond Operation If cond is true: *SP – – → PC 1 → ST (GIE). Else, continue. Operands None Opcode 31 24 23 16 8 7 0 15 01 1 1 1 0 0 0 0 cond 0 0 0 0 00 000 0 0 00 00 00 0 0 Description A conditional return is performed.
Return From Interrupt Conditionally RETIcond 13-199 Assembly Language Instructions Example RETINZ Before Instruction After Instruction PC 0456 PC 0123 SP 809830 SP 80982F ST 0 ST 2000 LUF 0 LUF 0 LV 0.
RETScond Return From Subroutine Conditionally 13-200 Syntax RETS cond Operation If cond is true: *SP– – → PC. Else, continue. Operands None Opcode 31 24 23 16 8 7 0 15 01 1 1 1 0 0 1 0 cond 0 0 0 00 0 0 0 0 0 0 00 0 0 0 0 0 0 Description A conditional return is performed.
Return From Subroutine Conditionally RETScond 13-201 Assembly Language Instructions Example RETSGE Before Instruction After Instruction PC 0123 PC 0456 SP 80983C SP 80983B LUF 0 LUF 0 LV 0 LV 0 UF 0 U.
RND Round Floating-Point V alue 13-202 Syntax RND src, dst Operation rnd( src ) → dst Operands src general addressing modes (G): 0 0 register (R n , 0 ≤ n ≤ 7) 0 1 direct 1 0 indirect (disp = 0.
Round Floating-Point V alue RND 13-203 Assembly Language Instructions Example RND R5,R2 Before Instruction After Instruction R2 00 0000 0000 R2 07 33C1 6F00 R5 07 33C1 6EEF R5 07 33C1 6EEF LUF 0 LUF 0 LV 0 LV 0 UF 0 UF 0 N 0 N 0 Z 0 Z 0 V 0 V 0 C 0 C 0 1.
ROL Rotate Left 13-204 Syntax ROL dst Operation dst left-rotated 1 bit → dst Operands dst register (R n , 0 ≤ n ≤ 27) Opcode 31 24 23 16 8 7 0 15 000 1 0 1 0 1 0 dst 1 1 0 0000 0 0 00 000 0 00 1 Description The contents of the dst operand are left rotated one bit and loaded into the dst register .
Rotate Left Through Carry ROLC 13-205 Assembly Language Instructions Syntax ROLC dst Operation dst left-rotated one bit through carry bit → dst Operands dst register (R n , 0 ≤ n ≤ 27) Opcode 31.
ROLC Rotate Left Through Carry 13-206 Example 2 ROLC R3 Before Instruction After Instruction R3 00 8000 4281 R3 00 0000 8502 LUF 0 LUF 0 LV 0 LV 0 UF 0 UF 0 N 0 N 0 Z 0 Z 0 V 0 V 0 C 0 C 1.
Rotate Right ROR 13-207 Assembly Language Instructions Syntax ROR dst Operation dst right-rotated one bit through carry bit → dst Operands dst register (R n , 0 ≤ n ≤ 27) Opcode 31 24 23 16 8 7 .
RORC Rotate Right Through Carry 13-208 Syntax RORC dst Operation dst right-rotated one bit through carry bit → dst Operands dst register (R n , 0 ≤ n ≤ 27) Opcode 31 24 23 16 8 7 0 15 00 0 1 0 1.
Repeat Block RPTB 13-209 Assembly Language Instructions Syntax RPTB src Operation src → RE 1 → ST (RM) Next PC → RS Operands src long-immediate addressing mode Opcode 31 24 23 16 8 7 0 15 01 1 0 0 0 0 1 src Description RPTB allows a block of instructions to be repeated RC register + 1 times with- out any penalty for looping.
RPTB Repeat Block 13-210 Example RPTB 127h Before Instruction After Instruction PC 0123 PC 0124 RE 0 RE 127 RS 0 RS 124 ST 0 ST 100 LUF 0 LUF 0 LV 0 LV 0 UF 0 UF 0 N 0 N 0 Z 0 Z 0 V 0 V 0 C 0 C 0 Because the block-repeat modes modify the program counter , no other instruction can modify the program counter at the same time.
Repeat Single Instruction RPTS 13-21 1 Assembly Language Instructions Syntax RPTS src Operation src → RC 1 → ST (RM) 1 → S Next PC → RS Next PC → RE Operands src general addressing modes (G).
RPTS Repeat Single Instruction 13-212 Example RPTS AR5 Before Instruction After Instruction AR5 00 00FF AR5 00 00FF PC 0123 PC 0124 RC 0 RC 0FF RE 0 RE 124 RS 0 RS 124 ST 0 ST 100 LUF 0 LUF 0 LV 0 LV .
Signal, Interlocked SIGI 13-213 Assembly Language Instructions Syntax SIGI Operation Signal interlocked operation. W ait for interlock acknowledge. Clear interlock. Operands None Opcode 31 24 23 16 8 7 0 15 00 0 1 0 0 1 0 10 00 0 00 00 0 0 0 000 0 0 000 00 0 0 Description An interlocked operation is signaled over XF0 and XF1.
STF Store Floating-Point V alue 13-214 Syntax STF src, dst Operation src → dst Operands src register (R n , 0 ≤ n ≤ 7) dst general addressing modes (G): 0 1 direct 1 0 indirect (disp = 0–255, IR0, IR1) Opcode 31 24 23 16 8 7 0 15 00 0 1 0 0 0 0 1 src G dst Description The src register is loaded into the dst memory location.
Store Floating-Point V alue, Interlocked STFI 13-215 Assembly Language Instructions Syntax STFI src, dst Operation src → dst Signal end of interlocked operation.
STFI Store Floating-Point V alue, Interlocked 13-216 Note: The STFI instruction is not interruptible because it completes when ready is signaled. See Section 7.
Parallel Store Floating-Point V alue STF||STF 13-217 Assembly Language Instructions Syntax STF src2, dst2 || STF src1 , dst1 Operation src2 → dst2 || src1 → dst1 Operands src1 register (R n 1, 0 .
STF||STF Parallel Store Floating-Point V alue 13-218 Example STF R4,*AR3 –– || STF R3,*++AR5 Before Instruction After Instruction R3 07 33C0 0000 R3 07 33C0 0000 R4 07 0C80 0000 R4 07 0C80 0000 AR.
Store Integer STI 13-219 Assembly Language Instructions Syntax STI src, dst Operation src → dst Operands src register (R n , 0 ≤ n ≤ 27) dst general addressing modes (G): 0 1 direct 1 0 indirect.
STII Store Integer , Interlocked 13-220 Syntax STII src, dst Operation src → dst Signal end of interlocked operation Operands src register (R n , 0 ≤ n ≤ 27) dst general addressing modes (G): 0 .
Parallel STI and STI STI||STI 13-221 Assembly Language Instructions Syntax STI src2, dst2 || STI src1, dst1 Operation src2 → dst2 || src1 → dst1 Operands src1 register (R n 1, 0 ≤ n 1 ≤ 7) dst.
STI||STI Parallel STI and STI 13-222 Example STI R0,*++AR2(IR0) || STI R5,*AR0 Before Instruction After Instruction R0 00 0000 00DC R0 00 0000 00DC R5 00 0000 0035 R5 00 0000 0035 AR0 80 98D3 AR0 80 9.
Subtract Integer With Borrow SUBB 13-223 Assembly Language Instructions Syntax SUBB src, dst Operation dst – src – C → dst Operands src general addressing modes (G): 0 0 register (R n , 0 ≤ n .
SUBB3 Subtract Integer With Borrow , 3-Operand 13-224 Syntax SUBB3 src2, src1, dst Operation src1 – src2 – C → dst Operands src1 3-operand addressing modes (T): 0 0 register (R n 1, 0 ≤ n 1 .
Subtract Integer With Borrow , 3-Operand SUBB3 13-225 Assembly Language Instructions Example SUBB3 R5,*AR5++(IR0),R0 Before Instruction After Instruction R0 00 0000 0000 R0 00 0000 0032 R5 00 0000 00C.
SUBC Subtract Integer Conditionally 13-226 Syntax SUBC src, dst Operation If ( dst – src ≥ 0): ( dst – src << 1) OR 1 → dst Else: dst << 1 → dst Operands src general addressing m.
Subtract Integer Conditionally SUBC 13-227 Assembly Language Instructions Example 1 SUBC @98C5h,R1 Before Instruction After Instruction R1 00 0000 04F6 R1 00 0000 00C9 DP 080 DP 080 LUF 0 LUF 0 LV 0 L.
SUBF Subtract Floating-Point V alue 13-228 Syntax SUBF src , dst Operation dst – src → dst Operands src general addressing modes (G): 0 0 register (R n , 0 ≤ n ≤ 7) 0 1 direct 1 0 indirect (di.
Subtract Floating-Point V alue SUBF 13-229 Assembly Language Instructions Example SUBF *AR0 –– (IR0),R5 Before Instruction After Instruction R5 07 33C0 0000 R5 05 1D00 0000 AR0 80 9888 AR0 80 9808 IR0 80 IR0 80 LUF 0 LUF 0 LV 0 LV 0 UF 0 UF 0 N 0 N 0 Z 0 Z 0 V 0 V 0 C 0 C 0 Data memory 809888h 70C8000 809888h 70C8000 3.
SUBF3 Subtract Floating-Point V alue, 3-Operand 13-230 Syntax SUBF3 src2, src1, dst Operation src1 – src2 → dst Operands src1 3-operand addressing modes (T): 0 0 register (R n 1, 0 ≤ n 1 ≤ 7) .
Subtract Floating-Point V alue, 3-Operand SUBF3 13-231 Assembly Language Instructions Example 1 SUBF3 *AR0 –– (IR0),*AR1,R4 Before Instruction After Instruction R4 00 0000 0000 R4 05 1D00 0000 AR0.
SUBF3||STF Parallel SUBF3 and STF 13-232 Syntax SUBF3 src1, src2, dst1 || STF src3, dst2 Operation src2 – src1 → dst1 || src3 → dst2 Operands src1 register (R n 1, 0 ≤ n 1 ≤ 7) src2 indirect.
Parallel SUBF3 and STF SUBF3||STF 13-233 Assembly Language Instructions Example SUBF3 R1,*–AR4(IR1),R0 || STF R7,*+AR5(IR0) Before Instruction After Instruction R0 00 0000 0000 R0 06 1B60 0000 R1 05.
SUBI Subtract Integer 13-234 Syntax SUBI src, dst Operation dst – src → dst Operands src general addressing modes (G): 0 0 register (R n , 0 ≤ n ≤ 27) 0 1 direct 1 0 indirect (disp = 0–255, .
Subtract Integer , 3-Operand SUBI3 13-235 Assembly Language Instructions Syntax SUBI3 src2, src1, dst Operation src1 – src2 → dst Operands src1 3-operand addressing modes (T): 0 0 register (R n 1,.
SUBI3 Subtract Integer , 3-Operand 13-236 Example 1 SUBI3 R7,R2,R0 Before Instruction After Instruction R0 00 0000 0000 R0 00 0000 0032 R2 00 0000 0866 R2 00 0000 0866 R7 00 0000 0834 R7 00 0000 0834 .
Parallel SUBI3 and STI SUBI3||STI 13-237 Assembly Language Instructions Syntax SUBI3 src1, src2, dst1 || STI src3, dst2 Operation src2 – src1 → dst1 || src3 → dst2 Operands src1 register (R n 1,.
SUBI3||STI Parallel SUBI3 and STI 13-238 Example SUBI3 R7,*+AR2(IR0),R1 || STI R3,*++AR7 Before Instruction After Instruction R1 00 0000 0000 R1 00 0000 00C8 R3 00 0000 0035 R3 00 0000 0035 R7 00 0000.
Subtract Reverse Integer With Borrow SUBRB 13-239 Assembly Language Instructions Syntax SUBRB src, dst Operation src – dst – C → dst Operands src general addressing modes (G): 0 0 register (R n .
SUBRF Subtract Reverse Floating-Point V alue 13-240 Syntax SUBRF src, dst Operation src – dst → dst Operands src general addressing modes (G): 0 0 register (R n , 0 ≤ n ≤ 7) 0 1 direct 1 0 ind.
Subtract Reverse Integer SUBRI 13-241 Assembly Language Instructions Syntax SUBRI src, dst Operation src – dst → dst Operands src general addressing modes (G): 0 0 register (R n , 0 ≤ n ≤ 27) .
SWI Software Interrupt 13-242 Syntax SWI Operation Performs an emulation interrupt Operands None Opcode 31 24 23 16 8 7 0 15 01 100 0 1 0 1 0 0 0 00 00 0 00 0 0 0 0 0 00 000 0 0 0 00 0 Description The SWI instruction performs an emulator interrupt. This is a reserved instruc - tion and should not be used in normal programming.
T rap Conditionally TRAPcond 13-243 Assembly Language Instructions Syntax TRAP cond N Operation 0 → ST(GIE) If cond is true: Next PC → *++SP , T rap vector N → PC.
TRAPcond T rap Conditionally 13-244 Example TRAPZ 16 Before Instruction After Instruction PC 0123 PC 0010 SP 809870 SP 809871 ST 0 ST 0 LUF 0 LUF 0 LV 0 LV 0 UF 0 UF 0 N 0 N 0 Z 0 Z 0 V 0 V 0 C 0 C 0 Data memory T rap V .
T est Bit Fields TSTB 13-245 Assembly Language Instructions Syntax TSTB src, dst Operation dst AND src Operands src general addressing modes (G): 0 0 register (R n , 0 ≤ n ≤ 27) 0 1 direct 1 0 ind.
TSTB T est Bit Fields 13-246 Example TSTB *–AR4(1),R5 Before Instruction After Instruction R5 00 0000 0898 R5 00 0000 0898 AR4 80 99C5 AR4 80 99C5 LUF 0 LUF 0 LV 0 LV 0 UF 0 UF 0 N 0 N 0 Z 0 Z 1 V 0.
T est Bit Fields, 3-Operand TSTB3 13-247 Assembly Language Instructions Syntax TSTB3 src2, src1 Operation src1 AND src2 Operands src1 3-operand addressing modes (T): 0 0 register (R n 1, 0 ≤ n 1 ≤.
TSTB3 T est Bit Fields, 3-Operand 13-248 Example 1 TSTB3 *AR5 –– (IR0),*+AR0(1) Before Instruction After Instruction AR0 80 992C AR0 80 992C AR5 80 9885 AR5 80 9805 IR0 80 IR0 80 LUF 0 LUF 0 LV 0 .
Bitwise-Exclusive OR XOR 13-249 Assembly Language Instructions Syntax XOR src, dst Operation dst XOR src → dst Operands src general addressing modes (G): 0 0 register (R n , 0 ≤ n ≤ 27) 0 1 dire.
XOR3 Bitwise-Exclusive OR, 3-Operand 13-250 Syntax XOR3 src2, src1, dst Operation src1 XOR src2 → dst Operands src1 3-operand addressing modes (T): 0 0 register (R n 1, 0 ≤ n 1 ≤ 27) 0 1 indirec.
Bitwise-Exclusive OR, 3-Operand XOR3 13-251 Assembly Language Instructions Example 1 XOR3 *AR3++(IR0),R7,R4 Before Instruction After Instruction R4 00 0000 0000 R4 00 0000 A53C R7 00 0000 FFFF R7 00 0.
XOR3||STI Parallel XOR3 and STI 13-252 Syntax XOR3 src2, src1, dst1 || STI src3, dst2 Operation src1 XOR src2 → dst1 || src3 → dst2 Operands src1 register (R n 1, 0 ≤ n 1 ≤ 7) src2 indirect ( .
Parallel XOR3 and STI XOR3||STI 13-253 Assembly Language Instructions Status Bits These condition flags are modified only if the destination register is R7 – R0. LUF Unaffected LV Unaffected UF 0 N MSB of the output Z 1 if a 0 output is generated; 0 otherwise V 0 C Unaffected OVM Operation is not affected by OVM bit value.
A-1 Appendix A Instruction Opcodes The opcode fields for all TMS320C3x instructions are shown in T able A–1. Bits in the table marked with a hyphen are defined in the individual instruction descriptions (see Chapter 13, Assembly Language Instructions ).
Instruction Opcodes A-2 T able A–1. TMS320C3x Instruction Opcodes Instruction 31 30 29 28 27 26 25 24 23 ABSF 0 0 0 0 0 0 0 0 0 ABSI 0 0 0 0 00001 ADDC 0 0 0 0 00010 ADDF 0 0 0 0 00011 ADDI 0 0 0 0 .
Instruction Opcodes A-3 Instruction Opcodes T able A–1. TMS320C3x Instruction Opcodes (Continued) Instruction 23 24 25 26 27 28 29 30 31 MPYI 0 0 0 0 1 0 1 0 1 NEGB 0 0 0 0 10110 NEGF 0 0 0 0 10111 .
Instruction Opcodes A-4 T able A–1. TMS320C3x Instruction Opcodes (Continued) Instruction 23 24 25 26 27 28 29 30 31 SUBRB 0 0 0 1 1 0 0 0 1 SUBRF 0 0 0 1 10010 SUBRI 0 0 0 1 10011 TSTB 0 0 0 1 1010.
Instruction Opcodes A-5 Instruction Opcodes T able A–1. TMS320C3x Instruction Opcodes (Continued) Instruction 23 24 25 26 27 28 29 30 31 RPTB 0 1 1 0 0 1 0 – – S W I 0110011–– B cond (D) †.
Instruction Opcodes A-6 T able A–1. TMS320C3x Instruction Opcodes (Continued) Instruction 23 24 25 26 27 28 29 30 31 ABSI||STI 1 1 0 0 1 0 1 – – ADDF3||STF 1 1 0 0 110–– ADDI3||STI 1 1 0 0 1.
B-1 Appendix A TMS320C31 Boot Loader Source Code This appendix contains the source code for the ’C31 boot loader . Appendix B.
TMS320C31 Boot Loader Source Code B-2 ************************************************************************ * C31BOOT – TMS320C31 BOOT LOADER PROGRAM * (C) COPYRIGHT TEXAS INSTRUMENTS INC., 1990 * * NOTE: 1. AFTER DEVICE RESET, THE PROGRAM IS SET TO WAIT FOR * THE EXTERNAL INTERRUPTS.
TMS320C31 Boot Loader Source Code B-3 TMS320C31 Boot Loader Source Code .global check .sect ”vectors” reset .word check int0 .word 809FC1h int1 .word 809FC2h int2 .word 809FC3h int3 .word 809FC4h xint0 .word 809FC5h rint0 .word 809FC6h .word 809FC7h .
TMS320C31 Boot Loader Source Code B-4 trap11 .word 809FEBh trap12 .word 809FECh trap13 .word 809FEDh trap14 .word 809FEEh trap15 .word 809FEFh trap16 .word 809FF0h trap17 .word 809FF1h trap18 .word 809FF2h trap19 .word 809FF3h trap20 .word 809FF4h trap21 .
TMS320C31 Boot Loader Source Code B-5 TMS320C31 Boot Loader Source Code NOP *AR1++(1) ; jump last half word from mem. word LDI sub_h,AR3 ; half word size subroutine ; address –> AR3 LSH 1,R1 ; test bit 4 of mem.
TMS320C31 Boot Loader Source Code B-6 LDI *+AR0(4Ch),R1 LDI R0,R0 ; test load address flag BNN end_s load_s STI R1,*AR4++(1) ; store new word to dest. address end_s RETSU ; return from subroutine .
C-1 Appendix A TMS320C32 Boot Loader Source Code This appendix includes a description of the ’C32 boot loader sequence of events and a listing of its source code. T opic Page C.1 Boot-Loader Source Code Description C-2 . . . . . . . . . . . . . . . .
Boot-Loader Source Code Description C-2 C.1 Boot-Loader Source Code Description Figure C–1 shows the boot loader program flow chart. The boot loader pro- gram starts by initializing three registers: AR7 , SP , and IR0 .
Boot-Loader Source Code Description C-3 TMS320C32 Boot Loader Source Code Figure C–1. Boot-Loader Flow Chart Start Initialize regist ers: AR7, SP , IR0 Serial boot? Serial initialize serial global c.
Boot-Loader Source Code Listing C-4 C.2 Boot-Loader Source Code Listing ********************************************************************************** * C32BOOT – TMS320C32 BOOT LOADER PROGRAM (143 words) March–96 * (C) COPYRIGHT TEXAS INSTRUMENTS INCORPORATED, 1994 v.
Boot-Loader Source Code Listing C-5 TMS320C32 Boot Loader Source Code * that to function properly, the boot loader program always expects 32-bit * data from 32-bit wide memory during the boot load operation. Valid boot * EPROM widths are : 1, 2, 4, 8, 16 and 32 bits.
Boot-Loader Source Code Listing C-6 * Test for INT3 and, if set exclusively, proceed with serial boot load. Else, * load AR3 with 1000h if INT0, 810000h if INT1 900000h if INT2. Also load , * appropriate boot strobe pointer ––> AR2 and force the boot strobe value to * reflect 32bit memory width.
Boot-Loader Source Code Listing C-7 TMS320C32 Boot Loader Source Code label4 SUBI 2,AR6 CMPI 0,AR6 ; set flags BN strobes ;*******; total # of mem reads = 32/R5 label5 CALLU read_m ; read memory once .
Boot-Loader Source Code Listing C-8 CALLU AR0 ; 10 – STRB1 LDI R1,R4 AND 6Ch,R1 ; dest mem strb pntr ––> AR4 OR3 AR7,R1,AR4 LSH –8,R4 ; dest memory strobe ––> R4 LDI R4,R3 LSH –16,.
Boot-Loader Source Code Listing C-9 TMS320C32 Boot Loader Source Code read_s0 TSTB 20h,IF ; look at RINT0 flag BZ read_s0 ; wait for receive buffer full AND 0FDFh,IF ; reset interrupt flag LDI *+AR7(4.
Boot-Loader Source Code Listing C-10 LDI 2,IOF ;*; assert data acknowledge ;*; (XF0 low to host) loop6 TSTB 80h,IOF ;*; wait for data not ready BZ loop6 ;*; (XF1 high from host) LDI 6,IOF ;*; deassert.
D-1 Appendix A Glossary A A0–A23: External address pin s for data/program memory or I/O devices. These pins are on the primary bus. address: The location of program code or data stored in memory . addressing mode: The method by which an instruction interprets its oper- ands to acquire the data it needs.
Glossary D-2 BK: Block-size register . A 32-bit register used by the ARAU in circular ad- dressing to specify the data block size. boot loader: An on-chip code that loads and executes programs receive.
Glossary D-3 Glossary data size: The number of bits (8, 16, or 32) used to represent a particular number . decode phase: The phase of the pipeline in which the instruction is decoded (identified). DMA coprocessor: A peripheral that transfers the contents of memory loca- tions independently of the processor (except for initialization).
Glossary D-4 I IACK: Interrupt acknowledge signal . An output signal indicating that an in- terrupt has been received and that the program counter is fetching the interrupt vector that will force the processor into an interrupt service rou- tine. IE: See internal interrupt enable register .
Glossary D-5 Glossary M machine cycle: See CPU cycle . mantissa: A component of a floating-point number consisting of a fraction and a sign bit. The mantissa represents a normalized fraction whose binary point is shifted by the exponent. maskable interrupt : A hardware interrupt that can be enabled or disabled through software.
Glossary D-6 O overflow flag (OV) bit: A status bit that indicates whether or not an arithme- tic operation has exceeded the capacity of the corresponding register . P PC: Program counte r . A register that contains the address of the next instruction to be fetched.
Glossary D-7 Glossary S short floating-point format: A 16-bit representation of a floating point num- ber with a 12-bit mantissa and a 4-bit exponent. short floating-point format for external 16-bit data: A 16-bit representa- tion of a floating point number with an 8-bit mantissa and an 8-bit expo- nent.
Glossary D-8 W wait state : A period of time that the CPU must wait for external program, data, or I/O memory to respond when it reads from or writes to that exter- nal memory .
Index Index-1 Index 16-bit-wide configured memory , TMS320C31 1 1-10 2-operand instruction 13-3 2-operand instruction word 8-25 3-operand addressing modes 2-17, 13-24–13-25 3-operand instruction 13-.
Index Index-2 arithmetic logic unit (ALU), definition D-1 assembler syntax expression, example 13-38 assembly language, instruction set 2-operand instructions 13-3 3-operand instructions 13-4 interloc.
Index Index-3 assembly language instructions (continued) normalize (NORM) 13-182–13-183 parallel instructions ABSF and STF 13-42 ABSI and STI 13-46 ADDF3 and STF 13-55 ADDI3 and STI 13-60–13-61 AN.
Index Index-4 bitwise-logical AND 13-62 3-operand 13-63 with complement (ANDN) 13-67 complement instruction (NOT) 13-184 OR instruction 13-188 block diagram, TMS320C3x 1-3 repeat-mode control bits 7-3.
Index Index-5 carry bit, definition D-2 carry flag 13-29 central processing unit. See CPU circular addressing 6-21–6-25 algorithm 6-23 buffer 6-21–6-25 definition D-2 FIR filters 6-24 operation 6-.
Index Index-6 data-rate timing operation fixed 12-36 burst mode 12-36 continuous mode 12-36 variable 12-39 burst mode 12-35 continuous mode 12-40 data-page pointer (DP) 2-10, 3-4 data-receive register.
Index Index-7 extended-precision (R7–R0) registers 3-3 definition D-3 floating-point format, definition D-3 external buses (expansion, primary) 2-19 interface control registers 9-2 memory map 9-6 ti.
Index Index-8 global-control register DMA 12-53–12-59 serial port 12-15, 12-17–12-21 timer 12-3, 12-4–12-6 H handshake 1 1-20 hardware interrupt, definition D-3 hit, definition D-3 hold cycles 9.
Index Index-9 interface enhanced memory , TMS320C32 2-19 expansion bus 2-19 primary bus 2-19 interlocked instructions 2-21 operations 7-13–7-20 busy-waiting loop 7-15 external flag pins (XF0, XF1) 7.
Index Index-10 logical shift instruction (LSH) 13-136 LOPOWER 7-51–7-52 timing 7-52 low-power control instructions 13-5 idle instruction (IDLE2) 13-1 10 LRU cache update 4-19 LSB, definition D-4 M m.
Index Index-1 1 MSB , definition D-5 MSTRB signal 9-3, 9-15 multiple processors, sharing global memory 7-13 multiplication, floating-point, examples 5-29–5-31 multiplier definition D-5 floating-poin.
Index Index-12 peripherals 12-1–12-68 DMA controller 12-48–12-68 CPU/DMA interrupt enable regis- ter 12-59–12-62 destination- and source-address regis- ters 12-57–12-59 global-control register.
Index Index-13 program (continued) RPTB instruction 7-4–7-5 RPTS instruction 7-5–7-6 reset operation 7-21–7-25 TMS320LC31 power management mode IDLE2 7-49–7-51 LOPOWER 7-51–7-52 memory 2-19 .
Index Index-14 repeat end-address (RE) register 3-17, 7-2 repeat mode, definition D-6 repeat modes 7-2–7-8 control algorithm 7-4 control bits 7-3 maximum number of repeats 7-3 nested block repeats 7.
Index Index-15 serial port (continued) loading 1 1-1 1 memory mapped locations for 12-17 operation configurations 12-29–12-31 port control register FSR/DR/CLKR 12-23–12-24 FSX/DX/CLKX 12-22–12-2.
Index Index-16 timer-period register , definition D-7 timing external interface expansion bus I/O cycles 9-21–9-36 primary bus cycles 9-15–9-20 external memory interface 9-15–9-38 TMS320C30 arch.
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